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veripool / verilog-perl

Verilog parser, preprocessor, and related tools for the Verilog-Perl package
https://www.veripool.org/verilog-perl
Artistic License 2.0
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Enum widths do not get reported by Verilog::SigParser #1107

Closed veripoolbot closed 7 years ago

veripoolbot commented 8 years ago

Author Name: Lalit Chhabra Original Redmine Issue: 1107 from https://www.veripool.org

Original Assignee: Lalit Chhabra

Hi, I am trying to use Verilog::SigParser to calculate sizes of system verilog data structures in my verilog code. The var() callback provides information on data structures and their members, but the width of enums does not show up in the data type in all cases. For example, when parsing the following code:

typedef enum logic [1:0] { A=2'h0, B=2'h1 } my_enum_e;

the var() callback gets the following list of arguments (comma separated):

MyParser=HASH(0xf08440),typedef,my_enum_e,module,,logic,,

The $data_type argument is reported as "logic", but I would expect something like "logic [1:0]". Is this intentional?

I have attached a git patch with a fix for correct data_type reporting of enums; could you please check and incorporate into the next release?

Thanks, Lalit Chhabra

veripoolbot commented 8 years ago

Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2016-11-10T00:08:24Z

Great, well done.

Pushed to git towards 3.421. I'll release in about 2 weeks if nothing else comes up.

veripoolbot commented 7 years ago

Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2016-11-24T13:31:11Z

In 3.422.