search

veripool / verilog-perl

Verilog parser, preprocessor, and related tools for the Verilog-Perl package
https://www.veripool.org/verilog-perl
Artistic License 2.0
121 stars 34 forks source link

Question: Interface Declared as reg #1163

Closed veripoolbot closed 7 years ago

veripoolbot commented 7 years ago

Author Name: Wilder Ness Original Redmine Message: 2245 from https://www.veripool.org

I have code where interfaces are declared in the port declaration part. How do I get rid of the reg declaration below?

module a ( input x, input y, output z, my_interface.some local_if )

 /*AUTOREG*/
 // Beginning of automatic regs (for this module's undeclared outputs)
 reg      my_interface;
 // End of automatics

 assign local_if.port_a = 1'b0;

endmodule