Issue handling replications in new parser

[veripoolbot]

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Author Name: Leon Medpum Original Redmine Issue: 1205 from https://www.veripool.org

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Git version: 5f176d451876f859bce9ce294a67e3874aa2dfe6

We have some verilog that looks like this:

module submod1 (
     input [3:0] net1
);
endmodule

module top ();
     wire neta;

     submod1 submod1
     (.net1 ({neta,
              {3{1'b0}} })
     );
endmodule

When trying to link this verilog, I get the error:

%Error: top1.sv:10: Unexpected length in size of integer constant: "{3{1'b0}}".

I checked IEEE.1364-2005 and this seems to be legal syntax as per section 5.1.14

I can make it work if I convert this to the following, but I don't have the ability to actually modify our netlist.

module submod1 (
     input [3:0] net1
);
endmodule

module top ();
     wire neta;

     submod1 submod1
     (.net1 ({neta,
              3'b0 })
     );
endmodule

It links fine.

[veripoolbot]

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Original Redmine Comment Author Name: Stefan Tauner (@stefanct) Original Date: 2017-09-12T16:20:45Z

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Leon Medpum wrote:

Git version: 5f176d451876f859bce9ce294a67e3874aa2dfe6

We have some verilog that looks like this: [...]

When trying to link this verilog, I get the error:

%Error: top1.sv:10: Unexpected length in size of integer constant: "{3{1'b0}}".

I checked IEEE.1364-2005 and this seems to be legal syntax as per section 5.1.14

I can make it work if I convert this to the following, but I don't have the ability to actually modify our netlist. [...]

It links fine.

Yes, replications are not supported with the pinselects option at the moment and I am not planning to implement them within the parser. The best option I see at the moment is to ignore them and copy them over as is so that it can be handled by user code if need be. The following patch accomplishes that.

@Wilson: I have noticed another bug though, specifically when handling nested concatenations. The golden sample in @t/35_sigparser_ps.out:1150@ is most likely not what we want. There the contents of @{someotherbus[2],someotherbus[2]}@ are kinda duplicated. It is returned by the pinselects function as

{'netname' => '{someotherbus[2],someotherbus[2]}'},
{'lsb' => 2,'msb' => 2,'netname' => 'someotherbus'},
{'lsb' => 2,'msb' => 2,'netname' => 'someotherbus'}

Instead of the two individual components only:

{'lsb' => 2,'msb' => 2,'netname' => 'someotherbus'},
{'lsb' => 2,'msb' => 2,'netname' => 'someotherbus'}

I have fixed both issues in the following branch on github: https://github.com/uastw-embsys/Verilog-Perl/compare/replications_concats

KR, Stefan

[veripoolbot]

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Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2017-09-12T23:42:55Z

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Leon, thanks for the report, and Stefan for the patch.

Pushed to git towards 3.443.

[veripoolbot]

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Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2017-09-21T22:49:04Z

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Fixed in 3.444.