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veripool / verilog-perl

Verilog parser, preprocessor, and related tools for the Verilog-Perl package
https://www.veripool.org/verilog-perl
Artistic License 2.0
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Question: Usage of '*' in verilog-library-directories #1395

Closed veripoolbot closed 5 years ago

veripoolbot commented 5 years ago

Author Name: ABC ABCDEF Original Redmine Message: 2929 from https://www.veripool.org

Hi All,

Can I use '' inside of the verilog-library-directories* ?

I mean, is it possible to use just a partial file to the module location and for the rest path to use just '*'?


Ex1:
// verilog-library-directories:("." "../../ips/axi_ic/synth/") 

For Ex1, can I rewrite it as the following?
// verilog-library-directories:("." "../../ips/*") 
<pre?

Thank you!
veripoolbot commented 5 years ago

Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2019-03-24T12:51:49Z

You can use * to mean a single wildcard, as with all of Linux it won't do a recursive decent to subdirectories.

Note usually using verilog-library-flags is preferred as that matches simulator syntax.

    // verilog-library-flags:("-y . -y ../../ips/axi_ic/synth/") 
so this should work
    // verilog-library-flags:("-y . -y ../../ips/axi_ic/*/") 
this won't
    // verilog-library-flags:("-y . -y ../../ips/*/")

However some simulators don't support wildcarding (with -y), and it can slow things down, so would probably discourage doing this.