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veripool / verilog-perl

Verilog parser, preprocessor, and related tools for the Verilog-Perl package
https://www.veripool.org/verilog-perl
Artistic License 2.0
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Question: how to split a port assignment to multiple lines? #1421

Closed veripoolbot closed 5 years ago

veripoolbot commented 5 years ago

Author Name: ABC ABCDEF Original Redmine Message: 2954 from https://www.veripool.org

Hi All,

Here is a port assignment, which I'd like to do in the AUTO_TEMPLATE (.in is the port name, the rest is the assigning statement): 

.in  ((nxt_st==IDLE | nxt_st==UPDATE) ? 'd0 : {sop|bfr_ctrl_dout[XMUL_BEW+3], eop|bfr_ctrl_dout[XMUL_BEW+2], soc|bfr_ctrl_dout[XMUL_BEW+1], eoc|bfr_ctrl_dout[XMUL_BEW], be[XMUL_BEW-1:0]}),
</code>

But, I'd like to split the assignment to multiple lines (like this way):

.in  ((nxt_st==IDLE | nxt_st==UPDATE) ? 'd0 : 
       {sop|bfr_ctrl_dout[XMUL_BEW+3], 
        eop|bfr_ctrl_dout[XMUL_BEW+2], 
        soc|bfr_ctrl_dout[XMUL_BEW+1], 
        eoc|bfr_ctrl_dout[XMUL_BEW], 
        be[XMUL_BEW-1:0]}),
</code>

The \ in the end of the line does not work... So, how to split the port assignment to the multiple lines?

Thank you!

veripoolbot commented 5 years ago

Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2019-04-29T09:17:32Z

You cannot split lines as you wish. Generally the best thing is to use a temporary wire. (Some coding guidelines even disallow expressions in pins and require this for readability).

.in  (in),
....

wire [n:0] in = (nxt_st==IDLE | nxt_st==UPDATE) ? 'd0 : 
       {sop|bfr_ctrl_dout[XMUL_BEW+3], 
        eop|bfr_ctrl_dout[XMUL_BEW+2], 
        soc|bfr_ctrl_dout[XMUL_BEW+1], 
        eoc|bfr_ctrl_dout[XMUL_BEW], 
        be[XMUL_BEW-1:0]};