Closed veripoolbot closed 5 years ago
Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2019-08-20T23:41:03Z
There us no current way to do this. The UVM begin/end are similar and so indent properly but are hardcoded in the source. You could make a local veraion with edits if need be.
Original Redmine Comment Author Name: j briquet Original Date: 2019-08-20T23:56:49Z
Hi Wilson,
Thanks for your answer, could you just guide me through the source code, so I can give it a try. Or is it pretty straightforward ?
Regards, Jean-Pierre
Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2019-08-27T17:29:13Z
Look for e.g. uvm_field_utils_begin/end and add your own macro similarly.
Original Redmine Comment Author Name: j briquet Original Date: 2019-08-28T22:46:20Z
Thanks Wilson,
I think it should be ok, i was able to locate where I can include my changes.
Regards, Jean-Pierre
Author Name: j briquet Original Redmine Message: 3048 from https://www.veripool.org
Hi all,
Does anyone know if it’s possible to keep auto-indent working, within custom macros that would delimit the beginning and end of a block in system verilog.
‘test_begin(mytest) $display(“myexample”); ‘test_end
Where :
‘define test_begin(test) module ‘’test; initial begin ‘define test_end end endmodule
Sorry for the back tick, i was using my smartphone when typing this post.
Jean-Pierre