Question: How to prevent AUTOOUTPUT from processing wires? - Githubissues

veripool / verilog-perl

Verilog parser, preprocessor, and related tools for the Verilog-Perl package

https://www.veripool.org/verilog-perl

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Question: How to prevent AUTOOUTPUT from processing wires? #1547

Closed veripoolbot closed 4 years ago

veripoolbot commented 4 years ago

Author Name: Shareef Jalloq Original Redmine Message: 3124 from https://www.veripool.org

Sorry, I found the answer to this question previously but my search skillz are failing me this time.

If I have a child module with an output that is used within the parent, how do I prevent that signal being added to the AUTOOUTPUT list within the parent?

veripoolbot commented 4 years ago

Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2019-10-22T11:33:22Z

Typically, add it to verilog-auto-output-ignore-regexp.