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veripool / verilog-perl

Verilog parser, preprocessor, and related tools for the Verilog-Perl package
https://www.veripool.org/verilog-perl
Artistic License 2.0
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How to prevent link errors on parameterised module instances using vhier? #1664

Closed sjalloq closed 4 years ago

sjalloq commented 4 years ago

Hi,

I'm trying to use vhier to build an XML tree of a design but I'm seeing errors for missing modules that are actually parameterised out. You have the link_read_nonfatal option but I don't want to use this. I want errors for missing modules that are used in the design. What's the flow for using vhier when a module, mod_b, isn't in the tree?

  generate
    if PARAM
      mod_a u_a ();
    else
      mod_b u_b ();
    end
  endgenerate
wsnyder commented 4 years ago

Sorry, but link_read_nonfatal is the only way to do this at present. Since Verilog-Perl does not do elaboration, it can't know what modules are used or not used based on parameters.

Perhaps if your design uses mostly synthesis constructs you can use Verilator --xml output instead (see it's examples directory).

wsnyder commented 4 years ago

Closing as answered, feel free to ask additional questions if needed.