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veripool / verilog-perl

Verilog parser, preprocessor, and related tools for the Verilog-Perl package
https://www.veripool.org/verilog-perl
Artistic License 2.0
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+define+ process function-like macros with errors. #1680

Closed elvenfarseer closed 1 year ago

elvenfarseer commented 1 year ago

While vppreproc adequately accepts function-like macros via command-line, it does no substitutions in (system)verilog file.

For example, we have following string in (system)verilog file: always_ff @(`MACRO(clk,rstn))

and we pass macro definition to the command-line: vppreproc +define+MACRO\(CLK,RSTN\)=\(posedge\ \(CLK\)\ or\ negedge\ \(RSTN\)\) file.sv --dump-defines

is processed as expected: `\``define MACRO(CLK,RSTN) (posedge (CLK) or negedge (RSTN))

But calling without --dump-defines: vppreproc +define+MACRO\(CLK,RSTN\)=\(posedge\ \(CLK\)\ or\ negedge\ \(RSTN\)\) file.sv

is parsed in exactly the same string as in source: always_ff @(`MACRO(clk,rstn))

wsnyder commented 1 year ago

+define (and -D) was not designed to be used with define functions; I didn't realize other tools even allowed that (at least some don't). Regardless, Verilog-Perl is in maintenance mode, so if you would like this fixed, please make a pull request including appropriate tests.