This reproduces in 3.480 and I don't see any related code changes in the 3.483 version. Continuous assignments in an interface cause a missing method error for new_contassign which exists on Verilog::Netlist::Module but not Verilog::Netlist::Interface
Can't locate object method "new_contassign" via package "Verilog::Netlist::Interface" at lib/site_perl/5.38.2/x86_64-linux-thread-multi/Verilog/Netlist/File.pm line 98.
Below is a trivial testcase script and a workaround inline which declares an empty method that does nothing when the parser encounters a assign in a interface. The Interface object does not track statements currently and I don't have any need of this either, but avoiding the error being raised during evaluation of Verilog with these structures would likely be preferable to the current behavior.
#! /usr/local/bin/perl
use Verilog::Netlist;
use strict; use warnings FATAL => qw(all); use 5.014;
open my $fh, '>', 'example.sv' or die $@;
printf "$Verilog::Netlist::VERSION\n";
printf {$fh} <<"EOF";
interface myif(input i);
logic j;
assign j = i;
endinterface
module mybuf (input a, output z);
assign z = a;
endmodule
EOF
close $fh;
if (0) {
eval "
package Verilog::Netlist::Interface {
sub new_contassign {
# Deliberately does nothing, workaround for missing method
}
}
";
}
my $nl = new Verilog::Netlist();
$nl->read_file(filename=>'example.sv');
This package is currently only in maintenance mode. If you'd like to contribute a pull to fix this it would be appreciated, otherwise it's not likely to get fixed. Thanks.
This reproduces in 3.480 and I don't see any related code changes in the 3.483 version. Continuous assignments in an interface cause a missing method error for new_contassign which exists on Verilog::Netlist::Module but not Verilog::Netlist::Interface
Can't locate object method "new_contassign" via package "Verilog::Netlist::Interface" at lib/site_perl/5.38.2/x86_64-linux-thread-multi/Verilog/Netlist/File.pm line 98.
Below is a trivial testcase script and a workaround inline which declares an empty method that does nothing when the parser encounters a assign in a interface. The Interface object does not track statements currently and I don't have any need of this either, but avoiding the error being raised during evaluation of Verilog with these structures would likely be preferable to the current behavior.