Question: Scope for AUTO_LISP?

[veripoolbot]

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Author Name: Shareef Jalloq Original Redmine Message: 1635 from https://www.veripool.org

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Hi there,

I'm trying to use verilog-auto-output-ignore-regexp inside an AUTO_LISP but am running into the issue that this seems to apply the ignore to all modules that have the same signal name. Is this behaviour intended? I thought it should only apply to module within which it is used?

In my case I have an output from a child module that I don't want exported from a parent module (it's currently unused and tied off to an unused_ok). What I'm seeing is that once I run AUTO's in the parent, if I subsequently run AUTO's in the child module, the output is also removed from the child module.

Thanks.

[veripoolbot]

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Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2015-07-10T12:41:19Z

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I suspect this is because you're using "setq" on a variable that isn't "buffer-local" which is a general emacs concept. Instead of setting it in AUTO_LISP put it in the Local Variables section at the bottom of your file and it should work.

[veripoolbot]

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Original Redmine Comment Author Name: Shareef Jalloq Original Date: 2015-07-10T12:46:58Z

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Thanks but I tried the other example in the FAQ pages and it had the same behaviour.

/*
    Local Variables:
    eval:(setq verilog-auto-output-ignore-regexp (concat
    "^\\(" 
    "signal1_.*" 
    "\\|signal2_.*" 
    "\\)$" 
    )))
    End:
*/

[veripoolbot]

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Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2015-07-10T12:58:15Z

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Like this, I'll fix the FAQ:

Local Variables:
verilog-auto-output-ignore-regexp: "^\\(signal1_.*\\|signal2_.*\\)$" 
End:

Or this

Local Variables:
verilog-auto-output-ignore-regexp: ""
eval:(setq verilog-auto-output-ignore-regexp (concat
"^\\(" 
"signal1_.*" 
"\\|signal2_.*" 
"\\)$" 
)))
End:

[veripoolbot]

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Original Redmine Comment Author Name: Shareef Jalloq Original Date: 2015-07-10T13:11:31Z

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OK, thanks, that seems to work but...

on the signals I tried it with, once I've removed the auto-output-ignore, it seems to be sticky. Even removing the internal auto-wires and re-running autos doesn't result in the outputs being reinstated. I actually had to quit xemacs before it would re-parse correctly.

[veripoolbot]

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Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2015-07-10T13:15:38Z

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That's right because the problem was it was incorrectly set globally.

[veripoolbot]

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Original Redmine Comment Author Name: Shareef Jalloq Original Date: 2015-07-10T13:47:10Z

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Sorry, I'm getting confused. Perhaps we're talking at cross purposes.

I've tried your updated code,

Local Variables:
verilog-auto-output-ignore-regexp: "^\\(signal1_.*\\|signal2_.*\\)$" 
End:

and it works nicely. But if I remove the verilog-auto-output-ignore-regexp, for example imagine I've now implemented the functionality external to this module and would like to export this signal as an output, the output ports don't get updated. As a counter example, I don't have to quit and reload xemacs for a change to an AUTO_TEMPLATE to take effect, I just re-run AUTO's and the change is reflected. This variable seems to be sticky until a quit and reload of xemacs.

[veripoolbot]

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Original Redmine Comment Author Name: Shareef Jalloq Original Date: 2015-07-10T14:04:43Z

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Here's a noddy example to highlight what behaviour I would have expected.

Thanks.

[veripoolbot]

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Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2015-07-12T23:56:00Z

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A local variable sticks until the buffer is deleted, just delete the buffer then reload the file. Sorry, but that's how Emacs works, verilog-mode can't change it. (AUTO_TEMPLATE is done by verilog-mode itself so it does it nicer.)

Alternatively set it empty.

Local Variables: verilog-auto-output-ignore-regexp: nil End:

[veripoolbot]

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Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2015-07-12T23:58:22Z

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This may be better as avoids a warning in newer Emacs:

Local Variables: verilog-auto-output-ignore-regexp: "" End:

[veripoolbot]

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Original Redmine Comment Author Name: Shareef Jalloq Original Date: 2015-07-13T07:23:01Z

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OK, thanks a lot. I understand the issue now. Cheers.

[veripoolbot]

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Original Redmine Comment Author Name: Yonatan Shoshan Original Date: 2018-10-24T12:20:07Z

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Hi Wilson, I wanted to know if there was a way to define more than one regexp for the output-ignore-regexp variable. For example:

// Local Variables:
// verilog-auto-output-ignore-regexp:"clust._core._cevax_debug_mode" "boot_latch_spare"
// End:

Thanks!

[veripoolbot]

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Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2018-10-24T14:47:22Z

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Make a regular expression which ORs the two subexpressions. "\(clust._core._cevax_debug_mode\|boot_latch_spare\)"