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veryl-lang / std

Standard Library of Veryl Hardware Description Language
Apache License 2.0
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LFSR #1

Closed nblei closed 8 months ago

nblei commented 8 months ago

I've added a Galois linear feedback shift register.

It is parameterizable by width of the shift register (SIZE), as well as the taps (TAPVEC).

Default tap vectors are given for LFSRs of size 2 through 64.

I have also added a SV testbench, and I have tested that the default LFSRs have maximal period for sizes up to 24 bits.

dalance commented 8 months ago

The SV testbench is useful as reference for Veryl's unit test feature. I'll focus that the testbench can be written by Veryl. It will be minimum viable product of unit test feature.

nblei commented 8 months ago

The SV testbench is useful as reference for Veryl's unit test feature. I'll focus that the testbench can be written by Veryl. It will be minimum viable product of unit test feature.

Is Veryl unit testing a feature that currently exists or one that you're working on? If the former, could you point me to the documentation on it?

dalance commented 8 months ago

Is Veryl unit testing a feature that currently exists or one that you're working on? If the former, could you point me to the documentation on it?

Not yet. So I'll merge this PR as is. After implementing unit test feature, I want to translate the testbench to Veryl.