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veryl-lang / std

Standard Library of Veryl Hardware Description Language
Apache License 2.0
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Enable naming lint #7

Closed dalance closed 2 months ago

dalance commented 3 months ago

The current modules follow almost same naming rule. So the explicit naming lint configuration can be applied.

[lint.naming]
case_enum          = "snake"
case_function      = "snake"
case_instance      = "snake"
case_interface     = "snake"
case_modport       = "snake"
case_module        = "snake"
case_package       = "snake"
case_parameter     = "screaming_snake"
case_port_inout    = "snake"
case_port_input    = "snake"
case_port_modport  = "snake"
case_port_output   = "snake"
case_reg           = "snake"
case_struct        = "snake"
case_union         = "snake"
case_var           = "snake"
case_wire          = "snake"
prefix_port_input  = "i_"
prefix_port_output = "o_"