[Feature] boolean type

[taichi-ishitani]

The boolean data type is useful to declare variables/parameters which mean on/off. Therefore, I'd like to introduce the boolean data type.

This is equivalent SV definition.

typedef enum logic {
  VERYL_FALSE = 1'b0,
  VERYL_TRUE  = 1'b1
} veryl_boolean;

[dalance]

Looks good. Which is better enum logic and simple logic?

enum logic can check assignment without cast in SystemVerilog side. But I think the result of compare operator can't be assigned directly. (Maybe can do it?)

var a: bool = (x > 1) as bool;

If Veryl insert the cast automatically, the transpiled code may be complicated.

veryl_boolean a;
assign a = veryl_boolean'(x > 1);

logic can do it, and type check can be handled at Veryl side. true and false will be converted to 0 and 1. It has less explicity than enum logic.

[taichi-ishitani]

Visivility of enum values on dump files is better than visivility of logic values so I prefer enum logic than logic a little bit. However, I don't care if you choose logic.

For readability, how about using following definition?

tyepdef logic veryl_boolean;
localparam veryl_boolean VERYL_TRUE  = 1'b1;
localparam veryl_boolean VERYL_FALSE = 1'b0;

[dalance]

parameter logic ENABLE_FUNC_A = 1;
parameter veryl_boolean ENABLE_FUNC_A = VERYL_TRUE;

For me, the first example is explicit sufficientlly, and the second is bit redundant. (Addisionally, identification between VERYL_TRUE and VERYL_FALSE is not easy because they are upper case.)

I think HDL doesn't have sufficient motivation to treat boolean as special type because part select generates boolean casually.