Interface Examples

[saturn77]

This is really a basic question and possibly feature request.

The Veryl tool as a transpiler is close the SystemVerilog conceptual design versus complete high level synthesis - and one of the features of SystemVerilog that I see as very valuable are interfaces, and tools such as Vivado now support synthesizing interfaces. My question is what features are supported in the Veryl interfaces? For example, are tasks and functions supported ?

Looking at the interface example in the documentation, it is not clear to me if they are supported. If these are supported, that is great, but if they are not supported, I think it would be worth considering to add them.

Tasks and functions in the interface make the interface sort of like a class, but actually are synthesizable. I see this as valuable for design reuse and encapsulation.

[dalance]

Sorry for the documentation missing. The complete syntax definition is below:

https://dalance.github.io/veryl/book/06_appendix/01_formal_syntax.html

InterfaceItem: VarDeclaration
             | LocalparamDeclaration
             | ModportDeclaration
             | InterfaceIfDeclaration
             | InterfaceForDeclaration
             | EnumDeclaration
             | StructDeclaration
             | InterfaceNamedBlock
             | FunctionDeclaration
             | ImportDeclaration
             | InitialDeclaration
             | FinalDeclaration
             ;

This shows that interface supports function. Task is still not implemented. I think it requires more consideration because tasks which consume time event may not be synthesizable.

[nblei]

SV tasks which do not consume time are semantically equivalent to void functions.