Back annotations

[nblei]

Dalance,

Not sure if there's interest, but a nice feature may be emitting SystemVerilog with back annotations of some sort. While this would help humans who are performing verification to identify links between emitted SV and Veryl, I think the bigger benefit here would be in enabling tools to automatically associate the emitted SV with the generating Veryl code. Consider, for example, a SV LSP which allows you to GOTO a veryl file, or a synthesis or APR script which can report timing/area/power/thermal violations at the Veryl level.

[dalance]

I'm interesting in this feature. One of the dissatisfied points of Chisel was missing machine readable source map.

The consideration points of this feature:

• Where are there annotations?
  • Inline of the generated source code
  • Separated files corresponding to the generated source codes
  • Single file
• What format does the annotations have?
  • text format ( ex. TOML/JSON/...)
  • binary format

The sourcemap of JavaScript seems to be useful as reference.

https://sourcemaps.info/spec.html https://www.bugsnag.com/blog/source-maps/

At the moment, I prefer "Single file" and "TOML format" with Base 64 VLQ encoded entries.

[dalance]

I'm tring to add source map support at #741. I adopted the source map format of JavaScript defined at https://sourcemaps.info/spec.html. This is because the format has large ecosystem in JS and Rust world.

For example, the following link is the result of delay.veryl in std by Source Map Visualization.

link

[nblei]

This is fantastic

[dalance]

I added a feature to remap path:line:col in verilator's log at veryl test. Now we can see where is root cause in Veryl's code easily.

%Error: /home/hatta/work/repos/veryl/testcases/sv/48_test.sv:11: Verilog $stop
        ^ from: /home/hatta/work/repos/veryl/testcases/veryl/48_test.veryl:4:18
[ERROR]       Failed test (test1)
[INFO ]    Compiling test (test2)
%Error: /home/hatta/work/repos/veryl/testcases/sv/48_test.sv:23:1: syntax error, unexpected endmodule
        ^ from: /home/hatta/work/repos/veryl/testcases/veryl/48_test.veryl:18:18
   23 | endmodule
      | ^~~~~~~~~
%Error: Cannot continue
[ERROR]       Failed compile (test2)
[INFO ]    Compiling test (test3)
%Error-PROCASSWIRE: /home/hatta/work/repos/veryl/testcases/sv/48_test.sv:31:17: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'a'
                    ^ from: /home/hatta/work/repos/veryl/testcases/veryl/48_test.veryl:26:18
                                                                              : ... note: In instance 'test3'
   31 |     always_comb a = 1;
      |                 ^
                    ... For error description see https://verilator.org/warn/PROCASSWIRE?v=5.024
%Error: Exiting due to 1 error(s)
        ... See the manual at https://verilator.org/verilator_doc.html for more assistance.

[nblei]

This is beautiful, and a fantastic example of why open source hardware development tools have a place.

On Fri, Jun 7, 2024, 5:25 AM Naoya Hatta @.***> wrote:

I added a feature to remap path:line:col in verilator's log at veryl test. Now we can see where is root cause in Veryl's code easily.

%Error: /home/hatta/work/repos/veryl/testcases/sv/48_test.sv:11: Verilog $stop ^ from: /home/hatta/work/repos/veryl/testcases/veryl/48_test.veryl:4:18 [ERROR] Failed test (test1) [INFO ] Compiling test (test2) %Error: /home/hatta/work/repos/veryl/testcases/sv/48_test.sv:23:1: syntax error, unexpected endmodule ^ from: /home/hatta/work/repos/veryl/testcases/veryl/48_test.veryl:18:18 23 | endmodule | ^~~~~ %Error: Cannot continue [ERROR] Failed compile (test2) [INFO ] Compiling test (test3) %Error-PROCASSWIRE: /home/hatta/work/repos/veryl/testcases/sv/48_test.sv:31:17: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'a' ^ from: /home/hatta/work/repos/veryl/testcases/veryl/48_test.veryl:26:18 : ... note: In instance 'test3' 31 | always_comb a = 1; | ^ ... For error description see https://verilator.org/warn/PROCASSWIRE?v=5.024 https://urldefense.com/v3/__https://verilator.org/warn/PROCASSWIRE?v=5.024__;!!DZ3fjg!_5ngvDLI-2pfp31Rkd-RgbByQXrDmiOGFZoLI38IRB5L3JGt2zbt50EihRUg1lL2YzGap-Voqqtu1qthMbY3JaESjGpf$ %Error: Exiting due to 1 error(s) ... See the manual at https://verilator.org/verilator_doc.html https://urldefense.com/v3/__https://verilator.org/verilator_doc.html__;!!DZ3fjg!_5ngvDLI-2pfp31Rkd-RgbByQXrDmiOGFZoLI38IRB5L3JGt2zbt50EihRUg1lL2YzGap-Voqqtu1qthMbY3JfdBAk_Y$ for more assistance.

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[dalance]

I'll merge #741, and this issue will be closed. The remaining features are moved to #776 because I think the feature to consume source map should be separated from Veryl compiler.