Independent library or binary from Veryl compiler to translate source position by source map is useful.
For example, the binary can translate the existing log or receive log through pipe like below:
$ resolver synthesis.log
$ ./simv | resolver
Independent library with C API may be useful to integrate to other EDA tools like Verilator, Yosys, and so on.
Independent library or binary from Veryl compiler to translate source position by source map is useful. For example, the binary can translate the existing log or receive log through pipe like below:
Independent library with C API may be useful to integrate to other EDA tools like Verilator, Yosys, and so on.
Related: #438