Enhance case statement/expression

veryl-lang / veryl

Veryl: A Modern Hardware Description Language

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Closed taichi-ishitani closed 2 weeks ago

taichi-ishitani commented 2 weeks ago

Case statement/expressoin
- use case inside/==? operator
- support range expression on case condition
- introduce limitation that case condition should be constant
  - this is to prevent mismatch between simulation and synthesis
Swich statement/expression
- this is for idiom of onehot csae statement
  - case (1'b1) ... endcase
- expression can be uesd for switch condition

resolve veryl-lang/veryl#643

dalance commented 2 weeks ago

Looks good! I'll merge this PR.