Open taichi-ishitani opened 2 weeks ago
Adding to this:
I think it would be nice to support the "name ranges". For example,
enum State {
Ready,
Run<6>,
Done
}
Adding to this:
I think it would be nice to support the "name ranges". For example,
enum State { Ready, Run<6>, Done }
Yes, I agree but I think you should create a new ticket for this feature.
For ease of checking enum label values, how about the following enum value rule?
I think this is a place where we'd want to follow the SV LRM very closely.
An enum variable or identifier will be automatically cast to a numerical type if used in a numeric expression.
Looking at the LRM, there are a number of things we still need to check for.
x
or z
assignment to an enum without an explicit data type or a 2-bit data type is an error: e.g., enum E { ...
or enum E: bit<4> { ...
. cannot have a x
or z
assignment.x
or z
assignment is illegal. E.g., enum E: logic<2> { IDLE=2'b00, XX=2'bxx, S1, S2 }
is illegal.enum ShouldError: u32 { S0, S1, S2 = 1, S3, }
is illegal .Value encodings are determined is as follows:
If no value is provided, then the first defined element is given value 0
and subsequent elements are incremented from the previous element. For enum type ranges, each instance of the range is treated as a separate element.
There is the limitation below for enum lebel values. Need to check if this limitation is satisfied.
From IEEE 1800-2023 6.19.2 Enumerated type ranges![image](https://github.com/veryl-lang/veryl/assets/2922232/02415981-684f-4f17-b957-1f7dd15e45ad)
Originally posted by @taichi-ishitani in https://github.com/veryl-lang/veryl/issues/771#issuecomment-2161792309