fixed multiple issues with expression checking

[nblei]

Fixes the issue raised by @nananapo in #785 but also fixes a number of other related issues.

1. Modports and interfaces were allowed to be in expressions if they were passed in to a module as a port. This has been fixed.
2. While user defined functions are not higher ordered type operators, some SystemVerilog System Functions are --- namely, ones which extract size information from a type. Thus, Enum, Union, Struct, UnionMember, and StructMember are suitable to be passed into functions with Kind SystemFunction.

[nblei]

Because I'm an idiot

On Thu, Jun 13, 2024, 7:37 PM Naoya Hatta @.***> wrote:

@.**** commented on this pull request.

In crates/analyzer/src/handlers/check_expression.rs https://urldefense.com/v3/__https://github.com/veryl-lang/veryl/pull/786*discussion_r1639076813__;Iw!!DZ3fjg!5qGyUMlwQqJ6XqiXcahwa8-yUJqqGw2eoFen36hUvMMb7rN82H7L6S2HFdODARSfKAA5DGWAzcJnqyHKu35epSl6N5Uu$ :

@@ -93,6 +125,19 @@ impl<'a> VerylGrammarTrait for CheckExpression<'a> { } } }

• } else if let Factor::ExpressionIdentifierFactorOpt(x) = arg {
• let expid = x.expression_identifier.as_ref();
• if let Ok(rr) = symbol_table::resolve(expid) {
• match rr.found.kind {
• SymbolKind::Function() | SymbolKind::ModportFunctionMember() => {
• self.call_stack_kind.pop();
• }
• SymbolKind::SystemFunction => {
• self.call_stack_kind.push(FunctionKind::System);

Why is this push not pop?

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[dalance]

Thanks. I'll merge this PR after resolving the conflict.