veryl-lang / veryl

Veryl: A Modern Hardware Description Language
Other
510 stars 24 forks source link

Change symbol of clock domain annotation #883

Closed dalance closed 3 months ago

dalance commented 3 months ago

Migration guide

Change the symbol of clock domnain annotation from ' to `.

module ModuleA (
    i_clk_a: input  'a clock,
    i_dat_a: input  'a logic,
    o_dat_a: output 'a logic,
    i_clk_b: input  'b clock,
    i_dat_b: input  'b logic,
    o_dat_b: output 'b logic,
) {
}
module ModuleA (
    i_clk_a: input  `a clock,
    i_dat_a: input  `a logic,
    o_dat_a: output `a logic,
    i_clk_b: input  `b clock,
    i_dat_b: input  `b logic,
    o_dat_b: output `b logic,
) {
}

Closes #882 Closes #863