veryl-lang / veryl

Veryl: A Modern Hardware Description Language
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Interface prototype #963

Open dalance opened 2 months ago

dalance commented 2 months ago

Interface prototype may be the same as concrete interface in almost cases.

proto interface ProtoA #(
    param X: u32,
) {
    var a: logic;

    modport A {
        a: input,
    }
}

interface InterfaceA for ProtoA #(
    param X: u32,
) {
    var a: logic;

    modport A {
        a: input,
    }
}

So generic bound by interface may be sufficient instead of adding interface prototype.

block rggen_connect_bit_field_if::<RIF: InterfaceA, FIF: InterfaceA, LSB: const, WIDTH: const> {
    assign  FIF.valid                 = RIF.valid;
    assign  FIF.read_mask             = RIF.read_mask[LSB+:WIDTH];
    assign  FIF.write_mask            = RIF.write_mask[LSB+:WIDTH];
    assign  FIF.write_data            = RIF.write_data[LSB+:WIDTH];
    assign  RIF.read_data[LSB+:WIDTH] = FIF.read_data;
    assign  RIF.value[LSB+:WIDTH]     = FIF.value;
}