vhda / verilog_systemverilog.vim

Verilog/SystemVerilog Syntax and Omni-completion
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Event trigger indentation issue #143

Closed antoinemadec closed 7 years ago

antoinemadec commented 7 years ago

Hi,

I noticed the following behavior when triggerring an event:

  initial
  begin
      ->e;  // indented one time too many
  end

Here is the diff in indent/verilog_systemverilog.vim I used to fix it:

-let s:vlog_open_statement = '\(\<or\>\|[<>:!=?&|^%/*+-]\)'
+let s:vlog_open_statement = '\(\<or\>\|[<>:!=?&|^%/*+]\|-[^>]\)'

I tried to run the tests and it seems OK. I hope this is correct. Could you please push it ?

Thanks again for the swell plugin, Antoine

vhda commented 7 years ago

Check the commit message format I'm using and create a Pull Request, please. If you have a fix, we can at least have your name on that commit :)

antoinemadec commented 7 years ago

My bad, will do ;)

vhda commented 7 years ago

Thanks for your contribution Antoine.