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vhda / verilog_systemverilog.vim

Verilog/SystemVerilog Syntax and Omni-completion
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Highlight issue with systemverilog: if : else if : else/else if #196

Open enots1010 opened 4 years ago

enots1010 commented 4 years ago

I saw there is a solution working for highlighting of following structure: if else if else

I was using the suggested way desribed here: https://github.com/vhda/verilog_systemverilog.vim/issues/121#issuecomment-252964308

However this is not entirely working.

In some cases the "else" in the end is not present. The construct only contains

if else if else if

unfortunately this is not highlighted when using match it plug in and the suggested solution from the link above.

Maybe somebody can support me here, because the vim reg expression are not that trivial in this case