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vhda / verilog_systemverilog.vim

Verilog/SystemVerilog Syntax and Omni-completion
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Add option to disable constant highlight #197

Closed yanma closed 4 years ago

yanma commented 4 years ago

Because the word which starts with uppercase letter is regarded as constant, signal name with the same rule is also highlighted. This is not applied with the name which starts with lowercase letter. Due to it, signal name is sometimes highlighted but sometimes not. I added an option to avoid this phenomenon which just disable constant highlight.

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vhda commented 4 years ago

Thanks @yanma!

yanma commented 4 years ago

Thank you for your quick response! I like this plug-in.