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vhda / verilog_systemverilog.vim

Verilog/SystemVerilog Syntax and Omni-completion
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Demo Request #199

Open BharadwajSP opened 4 years ago

BharadwajSP commented 4 years ago

Hi, This is absolute must-have plugin for Verification engineers. I could not find any demo of all the features available in it. it will be a great help for newcomers to take advantage. please point to me if anything available elsewhere.

thanks Keshava

vhda commented 4 years ago

Hi Keshava,

What kind of demo would you be looking for? Most of the information available on this plugin is in its README.md and the included Vim help text (:help verilog_systemverilog.txt). Is this not sufficient?

Best regards, Vitor

BharadwajSP commented 1 year ago

Hi Vitor,

I'm sorry I didn't check back on the comment/request I made earlier. I am looking for a Video Demo of most features specific to the SystemVerilog. for example, I have no idea how OMNI completion, error format follow instance will work. maybe because I never got it to work.! plus, when the project gets bigger at the cluster and SOC level where you have thousands of files or an individual file with thousands of lines of code( RAL files) it takes a lot of time to open itself with syntax fold on. So, is it possible to show us the features with DEMO and how to set it up, May be taking an example of UVM LIB and explaining all these would be a great help?

Thanks keshava.