Indent: Improve end-of-statement regexp to ignore increment/decrement - Githubissues

vhda / verilog_systemverilog.vim

Verilog/SystemVerilog Syntax and Omni-completion

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Indent: Improve end-of-statement regexp to ignore increment/decrement #233

Closed vhda closed 10 months ago

vhda commented 10 months ago

Fixes #232