vidor-libraries / VidorBitstream

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build_all.sh reports Error: Error opening system #3

Closed jomoengineer closed 5 years ago

jomoengineer commented 5 years ago

Hi, I am attempting to go through the steps outlined and I was able to get to the point of running build_all.sh under the MKRVIDOR4000_graphics folder but I am seeing the following error when I run this. NOTE: This is on Windows 10 x64


jomodev@jondevt110 /cygdrive/h/Development/Arduino_config/MKR_Vidor_4000/fpga/VidorBitstream/projects/MKRVIDOR4000_graphics
$ build_all.sh
2019.06.22.00:11:02 Error: Error opening system.

This is the version of Quartus Prime Shell that is installed.

$ quartus_sh --version
Quartus Prime Shell
Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
Copyright (C) 2018  Intel Corporation. All rights reserved.

Did I miss a step or something?

jomoengineer commented 5 years ago

Ah, okay I guess I missed the "chmod a+rw *" for Windows.

However, this still fails to build.


jomodev@jondevt110 /cygdrive/h/Development/Arduino_config/MKR_Vidor_4000/fpga/VidorBitstream/projects/MKRVIDOR4000_graphics
$ build_all.sh
2019.06.22.01:55:57 Info: Saving generation log to H:/Development/Arduino_config/MKR_Vidor_4000/fpga/VidorBitstream/projects/MKRVIDOR4000_graphics/build/MKRVIDOR4000_graphics_lite_sys/MKRVIDOR4000_graphics_lite_sys_generation.rpt
2019.06.22.01:55:57 Info: Starting: Create HDL design files for synthesis
2019.06.22.01:55:57 Info: qsys-generate H:\Development\Arduino_config\MKR_Vidor_4000\fpga\VidorBitstream\projects\MKRVIDOR4000_graphics\build\MKRVIDOR4000_graphics_lite_sys.qsys --synthesis=VERILOG --output-directory=H:\Development\Arduino_config\MKR_Vidor_4000\fpga\VidorBitstream\projects\MKRVIDOR4000_graphics\build\MKRVIDOR4000_graphics_lite_sys\synthesis --family="Cyclone 10 LP" --part=10CL016YU256C8G
2019.06.22.01:55:57 Info: Loading build/MKRVIDOR4000_graphics_lite_sys.qsys
2019.06.22.01:55:57 Info: Reading input file
2019.06.22.01:55:57 Info: Adding FBST_0 [FBST 1.0]
2019.06.22.01:55:57 Info: Parameterizing module FBST_0
2019.06.22.01:55:57 Info: Adding JTAG_BRIDGE [JTAG_BRIDGE 1.0]
2019.06.22.01:55:57 Info: Parameterizing module JTAG_BRIDGE
2019.06.22.01:55:57 Info: Adding MIPI_RX_ST_0 [MIPI_RX_ST 1.0]
2019.06.22.01:55:57 Info: Parameterizing module MIPI_RX_ST_0
2019.06.22.01:55:57 Info: Adding NEOPIXEL_0 [NEOPIXEL 1.0]
2019.06.22.01:55:57 Info: Parameterizing module NEOPIXEL_0
2019.06.22.01:55:57 Info: Adding QRCODE_FINDER_0 [QRCODE_FINDER 1.0]
2019.06.22.01:55:57 Info: Parameterizing module QRCODE_FINDER_0
2019.06.22.01:55:57 Info: Adding QUAD_ENCODER_0 [QUAD_ENCODER 1.0]
2019.06.22.01:55:57 Info: Parameterizing module QUAD_ENCODER_0
2019.06.22.01:55:57 Info: Adding SDRAM_ARBITER [SDRAM_ARBITER 1.0]
2019.06.22.01:55:57 Info: Parameterizing module SDRAM_ARBITER
2019.06.22.01:55:57 Info: Adding clk [clock_source 18.1]
2019.06.22.01:55:57 Info: Parameterizing module clk
2019.06.22.01:55:57 Info: Adding csi_i2c [o_i2c_master 1.0]
2019.06.22.01:55:57 Info: Parameterizing module csi_i2c
2019.06.22.01:55:57 Info: Adding flash_clk [clock_source 18.1]
2019.06.22.01:55:57 Info: Parameterizing module flash_clk
2019.06.22.01:55:57 Info: Adding flash_spi [tiny_spi 1.0]
2019.06.22.01:55:57 Info: Parameterizing module flash_spi
2019.06.22.01:55:57 Info: Adding hdmi_i2c [o_i2c_master 1.0]
2019.06.22.01:55:57 Info: Parameterizing module hdmi_i2c
2019.06.22.01:55:57 Info: Adding irq [altera_avalon_pio 18.1]
2019.06.22.01:55:57 Info: Parameterizing module irq
2019.06.22.01:55:57 Info: Adding mb [MAILBOX 1.0]
2019.06.22.01:55:57 Info: Parameterizing module mb
2019.06.22.01:55:57 Info: Adding nina_spi [tiny_spi 1.0]
2019.06.22.01:55:57 Info: Parameterizing module nina_spi
2019.06.22.01:55:57 Info: Adding nina_uart [arduino_16550_uart 18.1]
2019.06.22.01:55:57 Warning: nina_uart: Component type arduino_16550_uart is not in the library
2019.06.22.01:55:57 Info: Parameterizing module nina_uart
2019.06.22.01:55:57 Info: Adding nios2_gen2_0 [altera_nios2_gen2 18.1]
2019.06.22.01:55:57 Info: Parameterizing module nios2_gen2_0
2019.06.22.01:55:57 Info: Adding onchip_memory2_0 [altera_avalon_onchip_memory2 18.1]
2019.06.22.01:55:57 Info: Parameterizing module onchip_memory2_0
2019.06.22.01:55:57 Info: Adding pex_pio [PIO 1.0]
2019.06.22.01:55:57 Info: Parameterizing module pex_pio
2019.06.22.01:55:57 Info: Adding qspi [arduino_generic_quad_spi_controller2 18.1]
2019.06.22.01:55:57 Warning: qspi: Component type arduino_generic_quad_spi_controller2 is not in the library
2019.06.22.01:55:57 Info: Parameterizing module qspi
2019.06.22.01:55:57 Info: Adding sam_pio [PIO 1.0]
2019.06.22.01:55:57 Info: Parameterizing module sam_pio
2019.06.22.01:55:57 Info: Adding sam_pwm [PWM 1.0]
2019.06.22.01:55:57 Info: Parameterizing module sam_pwm
2019.06.22.01:55:57 Info: Adding sdram [altera_avalon_new_sdram_controller 18.1]
2019.06.22.01:55:57 Info: Parameterizing module sdram
2019.06.22.01:55:57 Info: Adding sysid_qsys_0 [altera_avalon_sysid_qsys 18.1]
2019.06.22.01:55:57 Info: Parameterizing module sysid_qsys_0
2019.06.22.01:55:57 Info: Adding timer_0 [altera_avalon_timer 18.1]
2019.06.22.01:55:57 Info: Parameterizing module timer_0
2019.06.22.01:55:57 Info: Adding vid [altera_clock_bridge 18.1]
2019.06.22.01:55:57 Info: Parameterizing module vid
2019.06.22.01:55:57 Info: Adding wm_pio [PIO 1.0]
2019.06.22.01:55:57 Info: Parameterizing module wm_pio
2019.06.22.01:55:57 Info: Building connections
2019.06.22.01:55:57 Info: Parameterizing connections
2019.06.22.01:55:57 Info: Validating
2019.06.22.01:55:58 Info: Done reading input file
2019.06.22.01:55:58 Info: MKRVIDOR4000_graphics_lite_sys.irq: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
2019.06.22.01:55:58 Error: MKRVIDOR4000_graphics_lite_sys.qspi: Component arduino_generic_quad_spi_controller2 18.1 not found or could not be instantiated
2019.06.22.01:55:58 Info: MKRVIDOR4000_graphics_lite_sys.sdram: SDRAM Controller will only be supported in Quartus Prime Standard Edition in the future release.
2019.06.22.01:55:58 Info: MKRVIDOR4000_graphics_lite_sys.sysid_qsys_0: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID
2019.06.22.01:55:58 Info: MKRVIDOR4000_graphics_lite_sys.sysid_qsys_0: Time stamp will be automatically updated when this component is generated.
2019.06.22.01:55:58 Warning: MKRVIDOR4000_graphics_lite_sys.JTAG_BRIDGE: Interrupt sender JTAG_BRIDGE.irq is not connected to an interrupt receiver
2019.06.22.01:55:58 Warning: MKRVIDOR4000_graphics_lite_sys.csi_i2c: Interrupt sender csi_i2c.interrupt_sender is not connected to an interrupt receiver
2019.06.22.01:55:58 Warning: MKRVIDOR4000_graphics_lite_sys.flash_spi: Interrupt sender flash_spi.irq is not connected to an interrupt receiver
2019.06.22.01:55:58 Warning: MKRVIDOR4000_graphics_lite_sys.hdmi_i2c: Interrupt sender hdmi_i2c.interrupt_sender is not connected to an interrupt receiver
2019.06.22.01:55:58 Warning: MKRVIDOR4000_graphics_lite_sys.JTAG_BRIDGE: JTAG_BRIDGE.event must be connected to an Avalon-MM master
2019.06.22.01:55:58 Error: MKRVIDOR4000_graphics_lite_sys.qspi.avl_mem: Data width must be of power of two and between 8 and 4096
2019.06.22.01:55:59 Info: MKRVIDOR4000_graphics_lite_sys: Generating MKRVIDOR4000_graphics_lite_sys "MKRVIDOR4000_graphics_lite_sys" for QUARTUS_SYNTH
2019.06.22.01:56:00 Info: Interconnect is inserted between master JTAG_BRIDGE.avalon_master and slave mb.mst because the master has address signal 32 bit wide, but the slave is 9 bit wide.
2019.06.22.01:56:00 Info: Interconnect is inserted between master JTAG_BRIDGE.avalon_master and slave mb.mst because the master has waitrequest signal 1 bit wide, but the slave is 0 bit wide.
2019.06.22.01:56:00 Info: Interconnect is inserted between master JTAG_BRIDGE.avalon_master and slave mb.mst because the master has readdatavalid signal 1 bit wide, but the slave is 0 bit wide.
2019.06.22.01:56:01 Error: null
jomoengineer commented 5 years ago

Okay, so I found after changing the file permission settings, I had to go back and run the apply_quartus_patches.sh script and rerun the make of makeCompositeBinary.

This is the output of running build_all.sh after doing the previous.


Info: Quartus Prime Shell was successful. 0 errors, 352 warnings
    Info: Peak virtual memory: 4626 megabytes
    Info: Processing ended: Sat Jun 22 02:28:30 2019
    Info: Elapsed time: 00:06:33
    Info: Total CPU time (on all processors): 00:00:05
create ram + flash app.ttf
Jun 22, 2019 2:28:30 AM - (INFO) elf2flash: args = --input=build/software/MKRVIDOR4000_graphics/MKRVIDOR4000_graphics_lite.elf --output=build/output_files/MKRVIDOR4000_graphics_lite.flash --base=0x008E0000 --end=0x008FFFFF --verbose --save
Jun 22, 2019 2:28:30 AM - (FINE) elf2flash: Starting
Jun 22, 2019 2:28:30 AM - (FINE) elf2flash: Done
projects
ip
cp: omitting directory './ip/GFX/arduino/Vidor_GFX/examples'
cp: omitting directory './ip/QUAD_ENCODER/arduino/VidorEncoder/examples'
cp: omitting directory './ip/NEOPIXEL/arduino/VidorNeopixel/examples'
cp: omitting directory './ip/MIPI_RX_ST/arduino/VidorCamera/examples'

Is this correct?

The resulting files are :


jomodev@jondevt110 /cygdrive/h/Development/Arduino_config/MKR_Vidor_4000/fpga/VidorBitstream/projects/MKRVIDOR4000_graphics
$ ls build/output_files/
MKRVIDOR4000_graphics_lite.asm.rpt
MKRVIDOR4000_graphics_lite.bin
MKRVIDOR4000_graphics_lite.done
MKRVIDOR4000_graphics_lite.fit.rpt
MKRVIDOR4000_graphics_lite.fit.smsg
MKRVIDOR4000_graphics_lite.fit.summary
MKRVIDOR4000_graphics_lite.flash
MKRVIDOR4000_graphics_lite.flow.rpt
MKRVIDOR4000_graphics_lite.jam
MKRVIDOR4000_graphics_lite.jbc
MKRVIDOR4000_graphics_lite.jdi
MKRVIDOR4000_graphics_lite.map.rpt
MKRVIDOR4000_graphics_lite.map.smsg
MKRVIDOR4000_graphics_lite.map.summary
MKRVIDOR4000_graphics_lite.pin
MKRVIDOR4000_graphics_lite.pof
MKRVIDOR4000_graphics_lite.rbf
MKRVIDOR4000_graphics_lite.sld
MKRVIDOR4000_graphics_lite.sof
MKRVIDOR4000_graphics_lite.sta.rpt
MKRVIDOR4000_graphics_lite.sta.summary
MKRVIDOR4000_graphics_lite.ttf
app.ttf
signature.h
facchinm commented 5 years ago

Hi @jomoengineer , it is the right outcome :slightly_smiling_face: In /cygdrive/h/Development/Arduino_config/MKR_Vidor_4000/fpga/VidorBitstream/distrib/ you should find the resulting Arduino library with all the API bindings and the bitstream in the right format. Copy it into your sketchbook and then you can use it in any sketch.

jomoengineer commented 5 years ago

Martino,

Thanks. I have replaced the existing VidorGraphics library files with the VidorBitstream/distrib bits and noticed there are some differences between the VidorBitstream code and the code that was installed via the Arduino IDE. Namely, the change for the setFont method since there were changes to the Vidor_GFX Class structure. I was able to get around this with the code I had already written but nothing was seen on HDMI monitor. I tried the VidorGraphics VidorDrawLogo Example from the Arduino IDE but that is much slower on the displaying of the text and is only showing part of the Arduino Logo text; just "tm" and "ino" from Arduino. This was working fine before, so I am not sure why it is not working now. Maybe it would be best I posted on the forum instead of here?

Thanks,

Jon

facchinm commented 5 years ago

The published code refers to the "next gen" Vidor library, with IP autodiscovery other goodies :slightly_smiling_face: So the slight difference in APIs and folder structure is due to this.

About the drawing speed, the problem is about NIOS softcore caches, which are not available if using Quartus Lite. Some people have been looking for a free, hardware based, solution (like https://github.com/vstrakh/VidorRaster and https://github.com/MinatsuT/VidorBitstream_GFX_HW) but they are not complete yet.

I'd close the discussion here to continue on the forum, since the technical problem seems fixed :wink: