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vijayakannamaneni / Verilog-Assignments

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Fix the bug in config driver task #2

Open ranjith-wisig opened 1 year ago

ranjith-wisig commented 1 year ago

https://github.com/vijayakannamaneni/Verilog-Assignments/blob/d90b59caa12b683a5d44593146baf3cdce9872bc/phase_compensation_test/phase_tb(1).sv#L102

  1. This task is not obeying AXIS protocol, please fix it
  2. Why are hardcoding the configs in the task, make them as an input arguments
ranjith-wisig commented 1 year ago
  1. Not only in this task, in every task the AXIS protocol is not followed exactly. Please fix in all the tasks.
vijayakannamaneni commented 1 year ago

Hard coding is okay , I will change that . But config task is following the axis protocol right .

ranjith-wisig commented 1 year ago

NO, It is not. Check the AXI protocol document.

On Thu, Aug 24, 2023 at 12:05 PM vijayakannamaneni @.***> wrote:

Hard coding is okay , I will change that . But config task is following the axis protocol right .

— Reply to this email directly, view it on GitHub https://github.com/vijayakannamaneni/Verilog-Assignments/issues/2#issuecomment-1691086370, or unsubscribe https://github.com/notifications/unsubscribe-auth/APGXGUPMACFWGUCDMCGMEQTXW3Y4VANCNFSM6AAAAAA34PFDVM . You are receiving this because you authored the thread.Message ID: @.***>

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vijayakannamaneni commented 1 year ago

If we have a valid data , we have to hold that till ready is high . And when ready is high we have to make valid as low and this continues .