Closed DrBwts closed 5 months ago
The port named ck_a0 in my design servers just as an ordinary GPIO output port. On the Arty A7 it's connected to the pin named A0. The purpose of this output port is described here. It is useful only if you intend to try the memory read speed benchmarking app provided in the the repository.
On Nexys A7 you can use any pin on board's Pmod connectors. For example, you can uncomment this line
#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { JA[1] }]; #IO_L20N_T3_A19_15 Sch=ja[1]
modify it to
set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { JA_1 }]; #IO_L20N_T3_A19_15 Sch=ja[1]
and rename port ck_a0 to JA_1 in the diagram.
Thankyou & thanks for the wonderful tutorial.
Hi
I followed your tutorial using the Nexys A7 board. I connected
ck_rt
to the CPU RESET button on the board by uncommenting the following line in the xdc file,That solved the first error but what I'm unclear about is the role of
ck_a0[0]
that remains unconstrained & the Nexys 7 xdc doesn't appear to have an equivalent pin to assign. Can I just uncomment one of the Pmod header pins?