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viktor-nikolov / MicroBlaze-DDR3-tutorial

Tutorial of a HW design of MicroBlaze using DDR3 RAM on Arty A7 board; DDR3 RAM speed test application
BSD 2-Clause "Simplified" License
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Bitstream generation failed #1

Closed DrBwts closed 5 months ago

DrBwts commented 5 months ago

Hi

I followed your tutorial using the Nexys A7 board. I connected ck_rt to the CPU RESET button on the board by uncommenting the following line in the xdc file,

##CPU Reset Button
set_property -dict { PACKAGE_PIN C12   IOSTANDARD LVCMOS33 } [get_ports { ck_rst }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn

That solved the first error but what I'm unclear about is the role of ck_a0[0] that remains unconstrained & the Nexys 7 xdc doesn't appear to have an equivalent pin to assign. Can I just uncomment one of the Pmod header pins?

##Pmod Headers
##Pmod Header JA
#set_property -dict { PACKAGE_PIN C17   IOSTANDARD LVCMOS33 } [get_ports { JA[1] }]; #IO_L20N_T3_A19_15 Sch=ja[1]
......
......
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viktor-nikolov commented 5 months ago

The port named ck_a0 in my design servers just as an ordinary GPIO output port. On the Arty A7 it's connected to the pin named A0. The purpose of this output port is described here. It is useful only if you intend to try the memory read speed benchmarking app provided in the the repository.

On Nexys A7 you can use any pin on board's Pmod connectors. For example, you can uncomment this line
#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { JA[1] }]; #IO_L20N_T3_A19_15 Sch=ja[1]
modify it to
set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { JA_1 }]; #IO_L20N_T3_A19_15 Sch=ja[1]
and rename port ck_a0 to JA_1 in the diagram.

DrBwts commented 5 months ago

Thankyou & thanks for the wonderful tutorial.