Open msnagar opened 1 year ago
In Vipin's project, the generated FIFO turns on the First Word Fall Through option, thus zero read latency. Your Verilog code is assuming this zero latency while reading. Due to the latency in FIFO circuit and you're using <=, however, the code can't capture the new data. This latency arises from transmission so it's not very large so you cannot see it in waveform diagram unless you zoom in very closely so it often gives an illusion that you can catch the new data at the current clock. As a side note, since delay statement (like #1) is not synthesizable, you can't simply use it to delay the assignment to catch the data in practical implementation; you have to wait until the next posedge of the clock even though the data will soon be available. The generated FIFO is active at rising edge of the clock and Vipin happened to do things at posedge, so this gives an illusion of one clock latency. That's how "Read Latency: 1" comes out when there is no FWFT feature in a FIFO, though the actual latency is not one-clock long. Maybe it is the case for your own FIFO which does not include FWFT. If so, you can either include FWFT feature in your FIFO design or read at the next clock if it is acceptable.
Below is my behavioral simulation. I let the rising edge to be at the middle of read enable signal, so you can see that the data is actually read out immediately after that moment. Also, as can be seen from the waveforms, the output data is zero before the first read, which is what's actually read, so your own FIFO always outputs 0.
Dear vipin, I test your code on the ZYNQ it is working fine with the generated FIFO. However, when I replace the FIFO with custom verilog code. It results always 0 output. I also tested the custom FIFO with AXI. It is working fine. FIFO code that I am using paste below.