Open hbrk opened 5 years ago
Description:Spelling Fault Steps to produce the issue:Digital Logic Design Lab->List of experiments->Adder Circuit->Manual Expected result:engine Actual result:enigne Screenshot:
Fixed Issue Commit Id.:4d2fbd2
Description:Spelling Fault Steps to produce the issue:Digital Logic Design Lab->List of experiments->Adder Circuit->Manual Expected result:engine Actual result:enigne Screenshot: