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[BUG REPORT] Virtual Labs Verification and interpretation of truth table for AND, OR, NOT, NAND, NOR, Ex-OR, Ex-NOR gates #1979

Open vlabs-bug opened 4 days ago

vlabs-bug commented 4 days ago

Bug Reported on 13 September, 9:45 GMT +5:50 in

Lab - Digital Electronics IITR Experiment - Verification and interpretation of truth table for AND, OR, NOT, NAND, NOR, Ex-OR, Ex-NOR gates Type(s) of Issue -

Additional info- thds

UserAgent: Mozilla/5.0 (Windows NT 10.0; Win64; x64) AppleWebKit/537.36 (KHTML, like Gecko) Chrome/128.0.0.0 Safari/537.36 Experiment Link - https://de-iitr.vlabs.ac.in/exp/truth-table-gates/simulation.html Email - ssrgyjryj1232@gmail.com