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Phase III Lab/Experiment(s) OnBoarding Request - Digital Electronics (IITR) #569

Open jaimathur opened 4 years ago

jaimathur commented 4 years ago

Lab OnBoarding Request

Use this to register your lab for hosting or update the list of experiments in the lab.

  1. Lab Repository: https://github.com/virtual-labs/digital-electronics-iitr

Optional

Fill this field to list the experiments that the lab should include

  1. List of Experiments and Repositories: | No.| Experiment Name | Experiment repository URL |

digital_electronics_iitr.pdf

sravanthimodepu commented 4 years ago

@jaimathur , please approve the following information

Repo Owner Details

Name - Dr R S Anand GitHub handle - jasbir56, priyanshi-a Email id - anandfee@gmail.com

Experiment Name Source URL Branch Tag Build Command

  1. Verification and interpretation of truth table for AND, OR, NOT, NAND. NOR, Ex-OR, Ex-NOR gates - http://vlabs.iitb.ac.in/gitlab/vlabs-dev-central-hosting/digital-electronics-iitr/verification-and-interpretation-truth-table-gates-iitr, Master Branch , v1.0.0, make all

  2. Construction of half/ full adder using XOR and NAND gates and verification of its operation- http://vlabs.iitb.ac.in/gitlab/vlabs-dev-central-hosting/digital-electronics-iitr/construction-half-full-adder-verification-of-operation-iitr, Master Branch , v1.0.0, make all

  3. To Study & Verify Half/Full Subtractor - http://vlabs.iitb.ac.in/gitlab/vlabs-dev-central-hosting/digital-electronics-iitr/half-full-subtractor-iitr, Master Branch , v1.0.0, make all

  4. Realization of logic functions with the help of Universal Gates (NAND, NOR) - http://vlabs.iitb.ac.in/gitlab/vlabs-dev-central-hosting/digital-electronics-iitr/realization-of-logic-functions-iitr, Master Branch , v1.0.0, make all

  5. Construction of a NOR gate latch and verification of its operation - http://vlabs.iitb.ac.in/gitlab/vlabs-dev-central-hosting/digital-electronics-iitr/construction-of-nor-gate-latch-iitr , Master Branch , v1.0.0, make all

  6. Verify the truth table of RS, JK, T and D flip-flops using NAND & NOR gates - http://vlabs.iitb.ac.in/gitlab/vlabs-dev-central-hosting/digital-electronics-iitr/verify-truth-table-of-flipflops-iitr, Master Branch , v1.0.0, make all

  7. Design and Verify the 4-Bit Serial In - Parallel Out Shift Registers - http://vlabs.iitb.ac.in/gitlab/vlabs-dev-central-hosting/digital-electronics-iitr/design-verify-four-bit-sipo-shift-registers-iitr , Master Branch , v1.0.0, make all

  8. Implementation and verification of decoder/de-multiplexer and encoder using logic gates - http://vlabs.iitb.ac.in/gitlab/vlabs-dev-central-hosting/digital-electronics-iitr/verification-decoder-demultiplexer-encoder-iitr, Master Branch , v1.0.0, make all

  9. Implementation of 4x1 multiplexer and 1x4 demultiplexer using logic gates - http://vlabs.iitb.ac.in/gitlab/vlabs-dev-central-hosting/digital-electronics-iitr/implementation-of-multiplexer-demultiplexer-iitr, Master Branch , v1.0.0, make all

  10. Design and verify the 4- Bit Synchronous/ Asynchronous Counter using JK Flip Flop - http://vlabs.iitb.ac.in/gitlab/vlabs-dev-central-hosting/digital-electronics-iitr/verify-four-bit-synchronous-asynchronous-counter-iitr, Master Branch

  11. Verify Binary to Gray and Gray to Binary conversion using NAND gates only - http://vlabs.iitb.ac.in/gitlab/vlabs-dev-central-hosting/digital-electronics-iitr/verify-binary-to-gray-and-gray-to-binary-conversion-iitr, Master Branch, v1.0.0, make all

  12. Verify the truth table of one bit and two bit comparator using logic gates - http://vlabs.iitb.ac.in/gitlab/vlabs-dev-central-hosting/digital-electronics-iitr/verify-truth-table-of-one-bit-and-two-bit-comparator-iitr, Master Branch, make all

pavanchow commented 4 years ago

@jaimathur We couldn't find GitHub handle for the above lab owner.

jaimathur commented 4 years ago

@pavanchow @priya100raman Github handle updated on excel sheet.

sravanthimodepu commented 4 years ago

@jaimathur

Hosted URL of Lab: http://de-iitr.vlabs.ac.in/ Branch: Master Tag: v1.0.0

Please get it approved by the owner

jaimathur commented 4 years ago

@priya100raman @sravanthimodepu

The lab has been verified by the developer.

pavanchow commented 3 years ago

@vlab-iitr @priyanshi-a Can you please provide Course Alignment for Digital Electronics (IITR) lab?

vlab-iitr commented 3 years ago

@pavanchow

Check the course alignment for Digital Electronics Lab. This is also mentioned in Round 0 file for Digital Electronics Lab.

vlab-iitr commented 3 years ago

@pavanchow

The codes for each experiment repo has not been pushed. Git error is shown it says :

remote: Permission to virtual-labs/exp-truth-table-gates-iitr.git denied to vlabiitr. fatal: unable to access 'https://github.com/virtual-labs/exp-truth-table-gates-iitr.git/': The requested URL returned error: 403

pavanchow commented 3 years ago

@vlab-iitr

vlabiitr GitHub handle is not a member of the repository. Please use vlab-iitr GitHub handle to push code.

priyanshi-a commented 3 years ago

@pavanchow Request to rehost the Digital Electronics Lab IITR with experiments:

  1. Verification and interpretation of truth table for AND, OR, NOT, NAND. NOR, Ex-OR, Ex-NOR gates - https://github.com/virtual-labs/exp-truth-table-gates-iitr with tag v1.0.0 https://github.com/virtual-labs/exp-truth-table-gates-iitr/releases/tag/v1.0.0

  2. Construction of half/ full adder using XOR and NAND gates and verification of its operation- https://github.com/virtual-labs/exp-half-full-adder-iitr with tag v1.0.0 https://github.com/virtual-labs/exp-half-full-adder-iitr/releases/tag/v1.0.0

  3. To Study & Verify Half/Full Subtractor - https://github.com/virtual-labs/exp-half-full-subtractor-iitr with tag v1.0.0 https://github.com/virtual-labs/exp-half-full-subtractor-iitr/releases/tag/v1.0.0

  4. Realization of logic functions with the help of Universal Gates (NAND, NOR) - https://github.com/virtual-labs/exp-realization-of-logic-functions-iitr with tag v1.0.0 https://github.com/virtual-labs/exp-realization-of-logic-functions-iitr/releases/tag/v1.0.0

  5. Construction of a NOR gate latch and verification of its operation - https://github.com/virtual-labs/exp-nor-gate-latch-iitr with tag v1.0.0 https://github.com/virtual-labs/exp-nor-gate-latch-iitr/releases/tag/v1.0.0

  6. Verify the truth table of RS, JK, T and D flip-flops using NAND & NOR gates - https://github.com/virtual-labs/exp-truth-tables-flip-flops-iitr with tag v1.0.0 https://github.com/virtual-labs/exp-truth-tables-flip-flops-iitr/releases/tag/v1.0.0

  7. Design and Verify the 4-Bit Serial In - Parallel Out Shift Registers - https://github.com/virtual-labs/exp-4bit-sipo-shift-register-iitr with tag v1.0.0 https://github.com/virtual-labs/exp-4bit-sipo-shift-register-iitr/releases/tag/v1.0.0

  8. Implementation and verification of decoder/de-multiplexer and encoder using logic gates - https://github.com/virtual-labs/exp-decoder-demultiplexer-encoder-iitr with tag v1.0.0 https://github.com/virtual-labs/exp-decoder-demultiplexer-encoder-iitr/releases/tag/v1.0.0

  9. Implementation of 4x1 multiplexer and 1x4 demultiplexer using logic gates - https://github.com/virtual-labs/exp-multiplexer-demultiplexer-iitr with tag v1.0.0 https://github.com/virtual-labs/exp-multiplexer-demultiplexer-iitr/releases/tag/v1.0.0

  10. Design and verify the 4- Bit Synchronous/ Asynchronous Counter using JK Flip Flop - https://github.com/virtual-labs/exp-4bit-synchronous-asynchronous-counter-iitr with tag v1.0.0 https://github.com/virtual-labs/exp-4bit-synchronous-asynchronous-counter-iitr/releases/tag/v1.0.0

  11. Verify Binary to Gray and Gray to Binary conversion using NAND gates only - https://github.com/virtual-labs/exp-binary-conversion-iitr with tag v1.0.0 https://github.com/virtual-labs/exp-binary-conversion-iitr/releases/tag/v1.0.0

  12. Verify the truth table of one bit and two bit comparator using logic gates - https://github.com/virtual-labs/exp-comparator-using-logic-gates-iitr with tag v1.0.0 https://github.com/virtual-labs/exp-comparator-using-logic-gates-iitr/releases/tag/v1.0.0

pavanchow commented 3 years ago

@priyanshi-a

Rehosted all the experiments of Digital Electronics Lab Hosted URL of Lab: http://de-iitr.vlabs.ac.in/ Branch: Main Tag: v1.0.0

Please check and approve.

priyanshi-a commented 3 years ago

@pavanchow

The course alignment file of Digital Electronics lab is not updated. Please check it.

https://de-iitr.vlabs.ac.in/digital-electronics-iitr/Course%20Alignment.html

pavanchow commented 3 years ago

@priyanshi-a

Updated the course alignment file of Digital Electronics. Please check it and approve.

https://de-iitr.vlabs.ac.in/digital-electronics-iitr/Course%20Alignment.html

priyanshi-a commented 3 years ago

@pavanchow Also, Exp6 Verify the truth table of RS, JK, T and D flip-flops using NAND & NOR gates - https://github.com/virtual-labs/exp-truth-tables-flip-flops-iitr with tag v1.0.0 https://github.com/virtual-labs/exp-truth-tables-flip-flops-iitr/releases/tag/v1.0.0 is not updated. Please check link: https://de-iitr.vlabs.ac.in/exp/truth-tables-flip-flops/

pavanchow commented 3 years ago

@priyanshi-a We are working on fixing this issue. We have reverted back to the older version of Exp6 Verify the truth table of RS, JK, T, and D flip-flops using NAND & NOR gates till it is fixed.

pavanchow commented 3 years ago

@priyanshi-a The .md files in the experiment directory of tag v1.0.0 are empty https://github.com/virtual-labs/exp-truth-tables-flip-flops-iitr/releases. Can you please create a new tag v1.0.1 with the sources.

priyanshi-a commented 3 years ago

@pavanchow

New tag v1.0.1 for exp-truth-tables-flip-flops-iitr : https://github.com/virtual-labs/exp-truth-tables-flip-flops-iitr/releases/tag/v1.0.1 Please check it.

pavanchow commented 3 years ago

@priyanshi-a

Hosted exp-truth-tables-flip-flops-iitr with tag v1.0.1

Please check and approve.

priyanshi-a commented 3 years ago

@pavanchow

The Digital Electronics Lab IITR has been updated and rehosted with all experiments.

BalammaBoya commented 3 years ago

@pavanchow Request to rehost the Digital Electronics Lab IITR with experiments: This issue also is used to host labs and their experiments that have been migrated to Pretest and Posttest questions ".js" format to ".json" format and updated .yml file.

| No.| Experiment Name | Experiment repository URL | Branch/Tag | |1. | Verification and interpretation of truth table for AND, OR, NOT, NAND. NOR, Ex-OR, Ex-NOR gates | https://github.com/virtual-labs/exp-truth-table-gates-iitr | v1.0.1 | | 2| Construction of half/ full adder using XOR and NAND gates and verification of its operation | https://github.com/virtual-labs/exp-half-full-adder-iitr | v1.0.1 | | 3. | To Study & Verify Half/Full Subtractor | https://github.com/virtual-labs/exp-half-full-subtractor-iitr | v1.0.1 | | 4. | Realization of logic functions with the help of Universal Gates (NAND, NOR) | https://github.com/virtual-labs/exp-realization-of-logic-functions-iitr | v1.0.1 | | 5.| Construction of a NOR gate latch and verification of its operation | https://github.com/virtual-labs/exp-nor-gate-latch-iitr | v1.0.1 | | 6. | Verify the truth table of RS, JK, T and D flip-flops using NAND & NOR gates | https://github.com/virtual-labs/exp-truth-tables-flip-flops-iitr| v1.0.2 | | 7. | Design and Verify the 4-Bit Serial In | Parallel Out Shift Registers | https://github.com/virtual-labs/exp-4bit-sipo-shift-register-iitr | v1.0.1 | | 8. | Implementation and verification of decoder/de-multiplexer and encoder using logic gates | https://github.com/virtual-labs/exp-decoder-demultiplexer-encoder-iitr | v1.0.1 | | 9. | Implementation of 4x1 multiplexer and 1x4 demultiplexer using logic gates | https://github.com/virtual-labs/exp-multiplexer-demultiplexer-iitr | v1.0.1 | | 10.| Design and verify the 4- Bit Synchronous/ Asynchronous Counter using JK Flip Flop | https://github.com/virtual-labs/exp-4bit-synchronous-asynchronous-counter-iitr| v1.0.1 | | 11.| Verify Binary to Gray and Gray to Binary conversion using NAND gates only | https://github.com/virtual-labs/exp-binary-conversion-iitr| v1.0.1 | | 12.| Verify the truth table of one bit and two bit comparator using logic gates | https://github.com/virtual-labs/exp-comparator-using-logic-gates-iitr | v1.0.1 |

pavanchow commented 3 years ago

@BalammaBoya Rehosted all the experiments of Digital Electronics Lab Hosted URL of Lab: http://de-iitr.vlabs.ac.in/

Please check and approve.

priyanshi-a commented 3 years ago

@pavanchow Request to rehost the some experiments of Digital Electronics Lab IITR due to some modifications as per requirement of experiment :

| Exp 8. | Implementation and verification of decoder/de-multiplexer and encoder using logic gates | https://github.com/virtual-labs/exp-decoder-demultiplexer-encoder-iitr | v1.0.2 |

| Exp 9. | Implementation of 4x1 multiplexer and 1x4 demultiplexer using logic gates | https://github.com/virtual-labs/exp-multiplexer-demultiplexer-iitr | v1.0.2 |

|Exp 11.| Verify Binary to Gray and Gray to Binary conversion using NAND gates only | https://github.com/virtual-labs/exp-binary-conversion-iitr | v1.0.2 |

pavanchow commented 3 years ago

@priyanshi-a Re-hosted all the mentioned experiments of Digital Electronics Lab Hosted URL of Lab: http://de-iitr.vlabs.ac.in/

Please check and approve.

priyanshi-a commented 3 years ago

@pavanchow Request to rehost the Digital Electronics Lab IITR with experiments: Lab has been updated as per reviews comment and resolved new tab issue.

| No.| Experiment Name | Experiment repository URL | Branch/Tag | |1. | Verification and interpretation of truth table for AND, OR, NOT, NAND. NOR, Ex-OR, Ex-NOR gates | https://github.com/virtual-labs/exp-truth-table-gates-iitr | v1.0.2 | https://github.com/virtual-labs/exp-truth-table-gates-iitr/releases/tag/v1.0.2 | 2| Construction of half/ full adder using XOR and NAND gates and verification of its operation | https://github.com/virtual-labs/exp-half-full-adder-iitr | v1.0.2 | https://github.com/virtual-labs/exp-half-full-adder-iitr/releases/tag/v1.0.2 | 3. | To Study & Verify Half/Full Subtractor | https://github.com/virtual-labs/exp-half-full-subtractor-iitr | v1.0.2 | https://github.com/virtual-labs/exp-half-full-subtractor-iitr/releases/tag/v1.0.2 | 4. | Realization of logic functions with the help of Universal Gates (NAND, NOR) | https://github.com/virtual-labs/exp-realization-of-logic-functions-iitr | v1.0.3 | https://github.com/virtual-labs/exp-realization-of-logic-functions-iitr/releases/tag/v1.0.3 | 5.| Construction of a NOR gate latch and verification of its operation | https://github.com/virtual-labs/exp-nor-gate-latch-iitr | v1.0.2 | https://github.com/virtual-labs/exp-nor-gate-latch-iitr/releases/tag/v1.0.2 | 6. | Verify the truth table of RS, JK, T and D flip-flops using NAND & NOR gates | https://github.com/virtual-labs/exp-truth-tables-flip-flops-iitr | v1.0.4 | https://github.com/virtual-labs/exp-truth-tables-flip-flops-iitr/releases/tag/v1.0.4 | 7. | Design and Verify the 4-Bit Serial In | Parallel Out Shift Registers | https://github.com/virtual-labs/exp-4bit-sipo-shift-register-iitr | v1.0.2 | https://github.com/virtual-labs/exp-4bit-sipo-shift-register-iitr/releases/tag/v1.0.2 | 8. | Implementation and verification of decoder/de-multiplexer and encoder using logic gates | https://github.com/virtual-labs/exp-decoder-demultiplexer-encoder-iitr | v1.0.4 | https://github.com/virtual-labs/exp-decoder-demultiplexer-encoder-iitr/releases/tag/v1.0.4 | 9. | Implementation of 4x1 multiplexer and 1x4 demultiplexer using logic gates | https://github.com/virtual-labs/exp-multiplexer-demultiplexer-iitr | v1.0.4 | https://github.com/virtual-labs/exp-multiplexer-demultiplexer-iitr/releases/tag/v1.0.4 | 10.| Design and verify the 4- Bit Synchronous/ Asynchronous Counter using JK Flip Flop | https://github.com/virtual-labs/exp-4bit-synchronous-asynchronous-counter-iitr| v1.0.3 | https://github.com/virtual-labs/exp-4bit-synchronous-asynchronous-counter-iitr/releases/tag/v1.0.3 | 11.| Verify Binary to Gray and Gray to Binary conversion using NAND gates only | https://github.com/virtual-labs/exp-binary-conversion-iitr | v1.0.3 | https://github.com/virtual-labs/exp-binary-conversion-iitr/releases/tag/v1.0.3 | 12.| Verify the truth table of one bit and two bit comparator using logic gates | https://github.com/virtual-labs/exp-comparator-using-logic-gates-iitr | v1.0.2 | https://github.com/virtual-labs/exp-comparator-using-logic-gates-iitr/releases/tag/v1.0.2

pavanchow commented 3 years ago

@priyanshi-a Re-hosted all the mentioned experiments of Digital Electronics Lab Hosted URL of Lab: https://de-iitr.vlabs.ac.in/

Please check and approve

priyanshi-a commented 3 years ago

@pavanchow

Request to re-host few experiments as per reviewer comments.

Exp1. | Verification and interpretation of truth table for AND, OR, NOT, NAND. NOR, Ex-OR, Ex-NOR gates | https://github.com/virtual-labs/exp-truth-table-gates-iitr | v1.0.3 | https://github.com/virtual-labs/exp-truth-table-gates-iitr/releases/tag/v1.0.3

Exp9. | Implementation of 4x1 multiplexer and 1x4 de-multiplexer using logic gates | https://github.com/virtual-labs/exp-multiplexer-demultiplexer-iitr | v1.0.5 | https://github.com/virtual-labs/exp-multiplexer-demultiplexer-iitr/releases/tag/v1.0.5

pavanchow commented 3 years ago

@priyanshi-a Re-hosted both the mentioned experiments of Digital Electronics Lab Hosted URL of Lab: https://de-iitr.vlabs.ac.in/

Please check and approve

ravikiran2020 commented 2 months ago

Rehosting the lab with Bug Report and Rating Feature