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Phase III Lab/Experiment(s) OnBoarding Request - Digital Logic Design IITB #612

Open jaimathur opened 4 years ago

jaimathur commented 4 years ago

Lab OnBoarding Request

Use this to register your lab for hosting or update the list of experiments in the lab.

  1. Lab Repository: https://github.com/virtual-labs/dld-pvgcoet-iitb

@priya100raman The information of this lab is in the Introduction Readme.md file.

Optional

Fill this field to list the experiments that the lab should include

  1. List of Experiments and Repositories: | No.| Experiment Name | Experiment repository URL |
priya100raman commented 4 years ago

@jaimathur could you please point us to the Introduction Readme.md file that you mention above? We do not see that in the : https://github.com/virtual-labs/dld-pvgcoet-iitb repo.

We hope that the Introduction Readme.md file follows the same format as the R0 pdf and captures the lab name, domain, list of exp, and other details needed by us to populate the lab pages.

jaimathur commented 4 years ago

@priya100raman Please find the link for the Introduction Readme.md file. http://vlabs.iitb.ac.in/gitlab/vlabs-dev-central-hosting/digital-logic-design-pvg/implementation-multiplexer-using-msi

This Readme.md file is present in each experiment repository of the lab.

sravanthimodepu commented 4 years ago

@jaimathur , please approve the following information

Repo Owner Details

Name - Prof. Santosh Noronha GitHub handle - Email id - noronha@iitb.ac.in

Experiment Name Source URL Branch Tag Build Command

  1. Eight-bit-digital-comparator-pvg - http://vlabs.iitb.ac.in/gitlab/vlabs-dev-central-hosting/digital-logic-design-pvg/eight-bit-digital-comparator-pvg, Master Branch, v1.0.0, make all

  2. Four-bit-digital-comparator-pvg - http://vlabs.iitb.ac.in/gitlab/vlabs-dev-central-hosting/digital-logic-design-pvg/four-bit-digital-comparator-pvg, Master Branch, v1.0.0, make all

  3. Binary-subtractor-pvg - http://vlabs.iitb.ac.in/gitlab/vlabs-dev-central-hosting/digital-logic-design-pvg/binary-subtractor-pvg, Master Branch, v1.0.0, make all

  4. Binary-adder-implementation-pvg -http://vlabs.iitb.ac.in/gitlab/vlabs-dev-central-hosting/digital-logic-design-pvg/binary-adder-implementation-pvg, Master Branch, v1.0.0, make all

  5. Binary-to-gray-code-converter-pvg - http://vlabs.iitb.ac.in/gitlab/vlabs-dev-central-hosting/digital-logic-design-pvg/binary-to-gray-code-converter-pvg, Master Branch, v1.0.0, make all

  6. Gray-to-binary-code-converter-pvg - http://vlabs.iitb.ac.in/gitlab/vlabs-dev-central-hosting/digital-logic-design-pvg/gray-to-binary-code-converter-pvg, Master Branch, v1.0.0, make all

  7. Four-variable-function-pvg - http://vlabs.iitb.ac.in/gitlab/vlabs-dev-central-hosting/digital-logic-design-pvg/four-variable-function-pvg, Master Branch, v1.0.0, make all

  8. Implementation-multiplexer-using-msi - http://vlabs.iitb.ac.in/gitlab/vlabs-dev-central-hosting/digital-logic-design-pvg/implementation-multiplexer-using-msi, Master Branch, v1.0.0, make all

sravanthimodepu commented 4 years ago

Please confirm the experiment order to host the lab

sravanthimodepu commented 4 years ago

@jaimathur

Please confirm the following Digital Logic Design lab content copied from the above mentioned README.md file:

  1. Objective: A digital trainer board is made available to the student on the simulator, which looks very similar to the laboratory setup. This lab is developed for digital logic design using the medium-scale integrated circuits. The procedure is demonstrated through a short video attached in the procedure. This lab basically uses the MSI ICs for building 8:1 multiplexer, any 4-variable function implementation, code converters, four bit binary adder and subtractor circuits. The students can also perform experiments based on comparator ICs. They can build the 4 bit and 8-bit comparators using MSI ICs. The best feature of this simulator is that it also has a provision to capture the timing diagrams for each of the input combinations and display the same. The additional features of this lab are it provides the student with the data sheets as well for a better understanding. it also has a tab to generate truth table and a debug option.

  2. Target Audience :

    • Students & Faculty

  3. Course Alignment :

    • Digital Electronics
    • Digital Logic Design

  4. Universities Mapped :

    • SPPU

Note: Please make sure that the lab name is correct before it is hosted. Otherwise there is a chance of losing analytics if we change the lab name after hosting the lab.

jaimathur commented 4 years ago

@priya100raman @sravanthimodepu

Please find the order of the experiments below:

  1. Implementation of 8:1 multiplexer using MSI ICs
  2. Design of four variable function using MSI ICs
  3. Design of Gray to Binary code converter using MSI ICs
  4. Design of Binary to Gray code converter using MSI ICs
  5. Implementation of binary adder using MSI ICs
  6. Design of binary subtractor using MSI ICs
  7. Implementation of 4-bit digital comparator using MSI ICs
  8. Design of 8 -bit digital comparator using MSI ICs

We have updated Target Audience in Introduction README.md file. Kindly update the same.

GitHub handle - jaimathur, pushpdeep

sravanthimodepu commented 4 years ago

@jaimathur

Hosted URL of Lab: https://dld-iitb.vlabs.ac.in/ Branch: Master Tag: v1.0.0

Please get it approved by the owner

priya100raman commented 4 years ago

@jaimathur

According the authoring convention used in all other Phase 3 experiments the content files like aim.md, theory.md, references.md are intended to contain just the content. These files should not contain the experiment name or the top level heading (like Aim, Theory etc.). The experiment name is given in experiment-name.md and should not be repeated anywhere else.

As you can also observe from the hosted link of the lab and experiments , the experiments of this lab are not following this convention. So, kindly make the necessary modifications to the markdown sources so that the consistency of the experiment interfaces can be maintained.

priya100raman commented 3 years ago

@jaimathur, could you please fix the above issues and state your approval so that we can share the hosted link with IITD.

jaimathur commented 3 years ago

@priya100raman, the above issues have been resolved.

priya100raman commented 3 years ago

@jaimathur , Could you please tag the fixed releases and raise the hosting request as per the format for each of the experiments- Experiment Name Source URL Branch Tag

jaimathur commented 3 years ago

@priya100raman

Kindly rehost the lab

  1. Implementation of 8:1 multiplexer using MSI ICs - http://vlabs.iitb.ac.in/gitlab/vlabs-dev-central-hosting/digital-logic-design-pvg/implementation-multiplexer-using-msi/tree/v1.0.1 , Master Branch, v1.0.1
  2. Design of four variable function using MSI ICs - http://vlabs.iitb.ac.in/gitlab/vlabs-dev-central-hosting/digital-logic-design-pvg/four-variable-function-pvg/tree/v1.0.1 , Master Branch, v1.0.1
  3. Design of Gray to Binary code converter using MSI ICs - http://vlabs.iitb.ac.in/gitlab/vlabs-dev-central-hosting/digital-logic-design-pvg/gray-to-binary-code-converter-pvg/tree/v1.0.1 , Master Branch, v1.0.1
  4. Design of Binary to Gray code converter using MSI ICs - http://vlabs.iitb.ac.in/gitlab/vlabs-dev-central-hosting/digital-logic-design-pvg/binary-to-gray-code-converter-pvg/tree/v1.0.1 , Master Branch, v1.0.1
  5. Implementation of binary adder using MSI ICs - http://vlabs.iitb.ac.in/gitlab/vlabs-dev-central-hosting/digital-logic-design-pvg/binary-adder-implementation-pvg/tree/v1.0.1 , Master Branch, v1.0.1
  6. Design of binary subtractor using MSI ICs - http://vlabs.iitb.ac.in/gitlab/vlabs-dev-central-hosting/digital-logic-design-pvg/binary-subtractor-pvg/tree/v1.0.1 , Master Branch, v1.0.1
  7. Implementation of 4-bit digital comparator using MSI ICs - http://vlabs.iitb.ac.in/gitlab/vlabs-dev-central-hosting/digital-logic-design-pvg/four-bit-digital-comparator-pvg/tree/v1.0.1 , Master Branch, v1.0.1
  8. Design of 8 -bit digital comparator using MSI ICs - http://vlabs.iitb.ac.in/gitlab/vlabs-dev-central-hosting/digital-logic-design-pvg/eight-bit-digital-comparator-pvg/tree/v1.0.1 , Master Branch, v1.0.1
pavanchow commented 3 years ago

@jaimathur

Hosted Digital Logic Design Lab URL: https://dld-iitb.vlabs.ac.in/

Please check and approve

jaimathur commented 3 years ago

@priya100raman Approved.

pavanchow commented 3 years ago

NOTE: This is just for reference.

Developer has merged this lab to a new lab, find the same in the source below, https://github.com/virtual-labs/engineers-forum/issues/721#issue-907868467

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