Experiment Repository Creation Request for Digital Logic Design Verilog Lab IIITH

[ravikiran2020]

Repository Creation Request

Use this to get your experiment repository created or updated on GitHub under Virtual Labs organization.

1. Coordinating Institute:IIITH

2. Approver’s Name:

3. Approved Proposal: This is Digital Logic Design Verilog lab for ext-ph3. Proposal yet to submit

4. Hosted url:

5. Primary GitHub Handle Details:

   Name: Raj

   GitHub Handle: raj-vlabs

   Email id:

6. Secondary GitHub Handle Details:

   Name: Ananya

   GitHub Handle: AnanyaV2004

   Email id:

[ravikiran2020]

Please find the links for Digital Logic Design Verilog Lab experiments and populate the repositories with sources of the experiments as detailed in Step 4 of the migration document.

1. Design of Adder circuit using Verilog- https://github.com/virtual-labs/exp-adder-circuit-verilog-iiith
2. Design of Multiplexer using Verilog - https://github.com/virtual-labs/exp-multiplexer-verilog-iiith
3. Design of ALU using Verilog - https://github.com/virtual-labs/exp-alu-verilog-iiith
4. Design of Counter using Verilog -https://github.com/virtual-labs/exp-counter-verilog-iiith
5. Design of Comparator using Verilog - https://github.com/virtual-labs/exp-comparator-verilog-iiith
6. Design of Latch and Flip Flops using Verilog - https://github.com/virtual-labs/exp-flip-flops-verilog-iiith
7. Design of Register using Verilog - https://github.com/virtual-labs/exp-register-verilog-iiith
8. Design of Multiplier using Verilog - https://github.com/virtual-labs/exp-multiplier-verilog-iiith