New daily trending repos in Verilog

vitalets commented 6 years ago

Subscribe to this issue and stay notified about new daily trending repos in Verilog!

github-trending-repos-bot commented 1 month ago

New daily trending repos in Verilog!

ekknod / pcileech-wifi pcileech-fpga with wireless card emulation

IObundle / iob-soc RISC-V System on Chip Template

github-trending-repos-bot commented 4 weeks ago

New daily trending repos in Verilog!

secworks / aes Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

github-trending-repos-bot commented 4 weeks ago

New daily trending repos in Verilog!

siliconcompiler / lambdalib Hardware abstraction library +1 stars today

github-trending-repos-bot commented 3 weeks ago

New daily trending repos in Verilog!

The-OpenROAD-Project / OpenROAD-flow-scripts OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/ +2 stars today

jotego / jtcores FPGA cores compatible with multiple arcade game machines and KiCAD schematics of arcade games. Working on MiSTer FPGA/Analogue Pocket

navaneethans / VLSI-LAB-EXP-1

nvdla / hw RTL, Cmodel, and testbench for NVDLA

github-trending-repos-bot commented 3 weeks ago

New daily trending repos in Verilog!

olofk / serv SERV - The SErial RISC-V CPU +1 stars today

RESMIRNAIR / FULL_SUBTRACTOR

github-trending-repos-bot commented 3 weeks ago

New daily trending repos in Verilog!

ultraembedded / riscv RISC-V CPU Core (RV32IM)

github-trending-repos-bot commented 3 weeks ago

New daily trending repos in Verilog!

rejunity / z80-open-silicon Z80 open-source silicon. Goal is to become a silicon proven, pin compatible, open-source replacement for classic Z80. +2 stars today

darklife / darkriscv opensouce RISC-V cpu core implemented in Verilog from scratch in one night! +2 stars today

os-fpga / Raptor Raptor end-to-end FPGA Compiler and GUI

os-fpga / Jira_Testcase

lnis-uofu / OpenFPGA An Open-source FPGA IP Generator

github-trending-repos-bot commented 3 weeks ago

New daily trending repos in Verilog!

TinyTapeout / tinytapeout-07 Tiny Tapeout 7

TinyTapeout / tinytapeout-06 Tiny Tapeout 06

github-trending-repos-bot commented 3 weeks ago

New daily trending repos in Verilog!

VerticalResearchGroup / miaow An open source GPU based off of the AMD Southern Islands ISA. +3 stars today

github-trending-repos-bot commented 2 weeks ago

New daily trending repos in Verilog!

OSCPU / yosys-sta

RESMIRNAIR / 4BIT_RIPPLECOUNTER

efabless / caravel_user_project https://caravel-user-project.readthedocs.io

github-trending-repos-bot commented 2 weeks ago

New daily trending repos in Verilog!

The-OpenROAD-Project / OpenROAD OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/ +1 stars today

github-trending-repos-bot commented 2 weeks ago

New daily trending repos in Verilog!

os-fpga / Raptor_Tools +1 stars today

ufrisk / pcileech-fpga FPGA modules used together with the PCILeech Direct Memory Access (DMA) Attack Software

github-trending-repos-bot commented 2 weeks ago

New daily trending repos in Verilog!

learn-cocotb / tutorial Complete tutorial code. +1 stars today

github-trending-repos-bot commented 2 weeks ago

New daily trending repos in Verilog!

AngeloJacobo / UberDDR3 Open-sourced DDR3 controller

zeroasiccorp / umi Universal Memory Interface (UMI)

github-trending-repos-bot commented 2 weeks ago

New daily trending repos in Verilog!

corundum / corundum Open source FPGA-based NIC and platform for in-network compute

github-trending-repos-bot commented 1 week ago

New daily trending repos in Verilog!

riscv-mcu / e203_hbirdv2 The Ultra-Low Power RISC-V Core +1 stars today

vortexgpgpu / vortex

ucb-bar / sha3

github-trending-repos-bot commented 1 week ago

New daily trending repos in Verilog!

Modos-Labs / Caster Open-source electrophoretics display controller. Mirror of https://gitlab.com/zephray/caster +1 stars today

navaneethans / VLSI-LAB-EXP-2

RESMIRNAIR / BCD_7SEGMENT

navaneethans / VLSI-LAB-EXP-3

github-trending-repos-bot commented 1 week ago

New daily trending repos in Verilog!

navaneethans / VLSI-LAB-EXP-4

RESMIRNAIR / JK_FLIPFLOP

SI-RISCV / e200_opensource Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

github-trending-repos-bot commented 1 week ago

New daily trending repos in Verilog!

IObundle / iob-picorv32 IOb_SoC version of the Picorv32 RISC-V Verilog IP core

IObundle / iob-cache Verilog Configurable Cache

RESMIRNAIR / ALU

github-trending-repos-bot commented 1 week ago

New daily trending repos in Verilog!

YosysHQ / picorv32 PicoRV32 - A Size-Optimized RISC-V CPU +2 stars today

ekknod / pcileech-multimedia spartan6 blackmagic +2 stars today

odriverobotics / ODriveHardware High performance motor control

github-trending-repos-bot commented 1 week ago

New daily trending repos in Verilog!

alexforencich / verilog-ethernet Verilog Ethernet components for FPGA implementation +1 stars today

simbricks / simbricks Main Repository for the SimBricks Modular Full-System Simulation Framework. +1 stars today

chili-chips-ba / openCologne Spicing up the first and only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples. +1 stars today

github-trending-repos-bot commented 6 days ago

New daily trending repos in Verilog!

alexforencich / verilog-axi Verilog AXI components for FPGA implementation +2 stars today

RESMIRNAIR / MOORE_1011

YosysHQ / yosys-oldtests Various larger test cases for yosys

os-fpga / yosys_verific_rs Yosys + (Optional) Verific Integration

github-trending-repos-bot commented 5 days ago

New daily trending repos in Verilog!

RESMIRNAIR / MEALY_1101

RESMIRNAIR / DIGI_LOCK

RESMIRNAIR / SR_FLIPFLOP

github-trending-repos-bot commented 4 days ago