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viveris / jtag-boundary-scanner

JTAG boundary scan debug & test tool.
GNU General Public License v3.0
118 stars 34 forks source link

How to use tool? #19

Open rjoshi2002 opened 3 months ago

rjoshi2002 commented 3 months ago

Hi, I am currently working on a Senior project where we have designed a custom jtag architecture based on the IEEE 1149.1 standard. We are attempting to test our design synthesized on an FPGA using a FT2232H probe. I came across this repository which seems like it would be useful for us to test our design. We even have a custom .BSDL file that we wrote. However we are unclear on how to get the program to compile and run. He is on a windows 11 laptop. We tried running make all which briefly opens a shell but immediately closes it. Some insight would be greatly appreciated.

AnttiLukats commented 1 month ago

Take ready compiled version, no need to compile from sources.