[Bug]: When I inference with a 1b model, tp2 latency is greater than tp1

[sitabulaixizawaluduo]

Your current environment

PyTorch version: 2.3.0+cu121
Is debug build: False
CUDA used to build PyTorch: 12.1
ROCM used to build PyTorch: N/A

OS: Ubuntu 22.04.4 LTS (x86_64)
GCC version: (Ubuntu 11.4.0-1ubuntu1~22.04) 11.4.0
Clang version: Could not collect
CMake version: version 3.29.5
Libc version: glibc-2.35

Python version: 3.10.12 (main, Nov 20 2023, 15:14:05) [GCC 11.4.0] (64-bit runtime)
Python platform: Linux-5.16.20-3.el7.x86_64-x86_64-with-glibc2.35
Is CUDA available: True
CUDA runtime version: Could not collect
CUDA_MODULE_LOADING set to: LAZY
GPU models and configuration: 
GPU 0: NVIDIA L40
GPU 1: NVIDIA L40
GPU 2: NVIDIA L40
GPU 3: NVIDIA L40
GPU 4: NVIDIA L40
GPU 5: NVIDIA L40
GPU 6: NVIDIA L40
GPU 7: NVIDIA L40

Nvidia driver version: 535.104.12
cuDNN version: Could not collect
HIP runtime version: N/A
MIOpen runtime version: N/A
Is XNNPACK available: True

CPU:
Architecture:                    x86_64
CPU op-mode(s):                  32-bit, 64-bit
Address sizes:                   46 bits physical, 57 bits virtual
Byte Order:                      Little Endian
CPU(s):                          128
On-line CPU(s) list:             0-127
Vendor ID:                       GenuineIntel
BIOS Vendor ID:                  Intel(R) Corporation
Model name:                      Intel(R) Xeon(R) Platinum 8358P CPU @ 2.60GHz
BIOS Model name:                 Intel(R) Xeon(R) Platinum 8358P CPU @ 2.60GHz
CPU family:                      6
Model:                           106
Thread(s) per core:              2
Core(s) per socket:              32
Socket(s):                       2
Stepping:                        6
CPU max MHz:                     3400.0000
CPU min MHz:                     800.0000
BogoMIPS:                        5200.00
Flags:                           fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb cat_l3 invpcid_single intel_ppin ssbd mba ibrs ibpb stibp ibrs_enhanced tpr_shadow vnmi flexpriority ept vpid ept_ad fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid cqm rdt_a avx512f avx512dq rdseed adx smap avx512ifma clflushopt clwb intel_pt avx512cd sha_ni avx512bw avx512vl xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local split_lock_detect wbnoinvd dtherm ida arat pln pts avx512vbmi umip pku ospke avx512_vbmi2 gfni vaes vpclmulqdq avx512_vnni avx512_bitalg tme avx512_vpopcntdq rdpid fsrm md_clear pconfig flush_l1d arch_capabilities
Virtualization:                  VT-x
L1d cache:                       3 MiB (64 instances)
L1i cache:                       2 MiB (64 instances)
L2 cache:                        80 MiB (64 instances)
L3 cache:                        96 MiB (2 instances)
NUMA node(s):                    2
NUMA node0 CPU(s):               0-31,64-95
NUMA node1 CPU(s):               32-63,96-127
Vulnerability Itlb multihit:     Not affected
Vulnerability L1tf:              Not affected
Vulnerability Mds:               Not affected
Vulnerability Meltdown:          Not affected
Vulnerability Spec store bypass: Mitigation; Speculative Store Bypass disabled via prctl
Vulnerability Spectre v1:        Mitigation; usercopy/swapgs barriers and __user pointer sanitization
Vulnerability Spectre v2:        Vulnerable: eIBRS with unprivileged eBPF
Vulnerability Srbds:             Not affected
Vulnerability Tsx async abort:   Not affected

Versions of relevant libraries:
[pip3] numpy==1.26.4
[pip3] nvidia-nccl-cu12==2.20.5
[pip3] torch==2.3.0
[pip3] triton==2.3.0
[conda] Could not collectROCM Version: Could not collect
Neuron SDK Version: N/A
vLLM Version: 0.5.0
vLLM Build Flags:
CUDA Archs: Not Set; ROCm: Disabled; Neuron: Disabled
GPU Topology:
GPU0    GPU1    GPU2    GPU3    GPU4    GPU5    GPU6    GPU7    NIC0    CPU Affinity    NUMA Affinity   GPU NUMA ID
GPU0     X      PIX     PXB     PXB     SYS     SYS     SYS     SYS     PXB     0-31,64-95      0               N/A
GPU1    PIX      X      PXB     PXB     SYS     SYS     SYS     SYS     PXB     0-31,64-95      0               N/A
GPU2    PXB     PXB      X      PXB     SYS     SYS     SYS     SYS     PXB     0-31,64-95      0               N/A
GPU3    PXB     PXB     PXB      X      SYS     SYS     SYS     SYS     PIX     0-31,64-95      0               N/A
GPU4    SYS     SYS     SYS     SYS      X      PIX     PXB     PXB     SYS     32-63,96-127    1               N/A
GPU5    SYS     SYS     SYS     SYS     PIX      X      PXB     PXB     SYS     32-63,96-127    1               N/A
GPU6    SYS     SYS     SYS     SYS     PXB     PXB      X      PXB     SYS     32-63,96-127    1               N/A
GPU7    SYS     SYS     SYS     SYS     PXB     PXB     PXB      X      SYS     32-63,96-127    1               N/A
NIC0    PXB     PXB     PXB     PIX     SYS     SYS     SYS     SYS      X 

Legend:

  X    = Self
  SYS  = Connection traversing PCIe as well as the SMP interconnect between NUMA nodes (e.g., QPI/UPI)
  NODE = Connection traversing PCIe as well as the interconnect between PCIe Host Bridges within a NUMA node
  PHB  = Connection traversing PCIe as well as a PCIe Host Bridge (typically the CPU)
  PXB  = Connection traversing multiple PCIe bridges (without traversing the PCIe Host Bridge)
  PIX  = Connection traversing at most a single PCIe bridge
  NV#  = Connection traversing a bonded set of # NVLinks

NIC Legend:

  NIC0: mlx5_bond_0```

### 🐛 Describe the bug

Finetuning a 1B model based on llama2 with
num_head=20,
num_layers=20,
head_size=128

When I use vllm0.5.0post1 tp1 to infer single data(input length 1024, output length 64), TPOT is around 6.3ms but when tp2, TPOT is around 6.9ms.
What is the reason for this.

[mgoin]

Hi @sitabulaixizawaluduo, let's break down what's happening with your 1B model and tensor parallelism (TP):

• GPU Memory: Each L40 GPU has 48GB of memory, which is more than enough for a 1B parameter model. You don't really need TP for memory reasons here to reach a large context length and/or batch size.
• TP and PCIe: Running TP across PCIe-connected GPUs isn't ideal for latency, especially with smaller models. PCIe isn't optimized for the low-latency communication TP requires in your case.
• Latency Difference: The gap between 6.3ms (TP=1) and 6.9ms (TP=2) is small and could be within normal performance variation.

To better evaluate the impact of TP:

• Increase your batch size to see more clear compute benefits.
• Run multiple trials and average the results.
• Test with larger output lengths or input sizes.

For a 1B model, TP overhead might outweigh benefits, especially with small batches or short sequences. The inter-GPU communication can introduce latencies that aren't offset by parallel processing at this scale.

To optimize inference latency, consider quantization like GPTQ to 8bit or 4bit weights. Let us know if you have any questions or if you discover anything interesting in your further tests.

[sitabulaixizawaluduo]

Hi @sitabulaixizawaluduo, let's break down what's happening with your 1B model and tensor parallelism (TP):

• GPU Memory: Each L40 GPU has 48GB of memory, which is more than enough for a 1B parameter model. You don't really need TP for memory reasons here to reach a large context length and/or batch size.
• TP and PCIe: Running TP across PCIe-connected GPUs isn't ideal for latency, especially with smaller models. PCIe isn't optimized for the low-latency communication TP requires in your case.
• Latency Difference: The gap between 6.3ms (TP=1) and 6.9ms (TP=2) is small and could be within normal performance variation.

To better evaluate the impact of TP:

• Increase your batch size to see more clear compute benefits.
• Run multiple trials and average the results.
• Test with larger output lengths or input sizes.

For a 1B model, TP overhead might outweigh benefits, especially with small batches or short sequences. The inter-GPU communication can introduce latencies that aren't offset by parallel processing at this scale.

To optimize inference latency, consider quantization like GPTQ to 8bit or 4bit weights. Let us know if you have any questions or if you discover anything interesting in your further tests.

Yes, it should look like the communication overhead is greater than the computation, leading to an increasing latency at this point. But when testing with LMDeploy, I found that TPOT's can reach almost exponential reduction, that's why I'm confused about this issue