How does SPI mode3 imitate SWD read-operation?

[llinjupt]

Hi talpachen,

Thanks for your great work at first. Here I have got a bit confused by the timing and hope you are able to clarify.

I have noticed that GD32F3X0 SPI is configured as MODE3 (both CKPL and CKPH are set), see swd.c: · SPI_CTL0(SWD_SPI_BASE) |= SPI_CTL0_MSTMOD | SPI_CTL0_SWNSSEN | SPI_CTL0_SWNSS | SPI_CTL0_LF | SPI_CTL0_CKPL | SPI_CTL0_CKPH;`

Refer to the SWD protocol, target device always put bit on(after) Rising edge of CLK while host tries to read data. But at the same time, SPI MODE3 always try to sample data on Rising edge, too, so it seems here is a competitive condition. If SCK goes high from low which means it will sample data from MISO, but the data is not ready (at least it is not steady) because the rising signal just tells target to put the data on.

Thanks in advance.

[talpachen]

确实如此，读操作部分并不满足时序要求。 之前在测试中未发现这个问题，可能是因为在上升沿之后目标芯片完成WRITE操作要快于SPI READ。