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A Just-In-Time Compiler for Verilog from VMware Research
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EventExpand pass generates code which doesn't type-check #150

Closed eschkufz closed 5 years ago

eschkufz commented 5 years ago

Overview

The EventExpand pass replaces wildcard event controls with the set of variables that are read within the enclosing timing control statement. When one of those variables is an array, the pass places a full part-select in the event control.

For example:

reg[31:0] r[1:0][1:0];
reg r10;

always @* begin
  r10 <= r[1][0];
end

Becomes

always @(r[1:0][1:0]) begin
  r10 <= r[1][0];
end

When it should become

always @(r) begin
  r10 <= r[1][0];
end

Deliverables