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A Just-In-Time Compiler for Verilog from VMware Research
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Misbehaving operator >> #152

Closed eschkufz closed 5 years ago

eschkufz commented 5 years ago

Overview

There is a bug in the implementation of operator >>. Specifically, shift amounts in excess of the bit-width of the target variable produce undefined behavior. A minimal example is below.

eg[54:0] subtrahend = 55'h7bcb43d769f764; 
reg[10:0] exponent_diff = 11'h056;

initial begin
  $display("%h >> %d = %h", subtrahend, exponent_diff, (subtrahend >> exponent_diff));
end

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