Support for concatenations in lhs of assignments

vmware-archive / cascade

A Just-In-Time Compiler for Verilog from VMware Research

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Support for concatenations in lhs of assignments #167

Closed eschkufz closed 4 years ago

eschkufz commented 4 years ago

Overview

A previous ticket added support for parsing assignments with concatenations on the left hand side of an assignment. Let's add simulation support as well.

Deliverables

[ ] sw support for concatenations on lhs of assignments