The code in src/verilog/analyze/constant.h assumes that if every identifier in an expression is a constant, then the expression is a constant as well. There’s no special logic for feof expressions, so when you check $feof(STDIN), it sees that STDIN is a constant localparam and assumes that the expression must be as well.
When we do the constant propagation pass, we use this check to determine whether we can replace an expression by a constant. If you’ve got a check against $feof(STDIN), we assume it’s a constant and then blow away the else condition of the check and make sure that the if branch is always taken.
By creating a variable and assigning it to STDIN, you can get around this, because the expression technically isn’t a constant. Technically. If you declare a register and never assign a value to it, we really should be calling it a constant, but that’s beside the point.
Deliverables
[ ] Fix analysis which concludes $feof(constant) is a constant.
Overview
The code in src/verilog/analyze/constant.h assumes that if every identifier in an expression is a constant, then the expression is a constant as well. There’s no special logic for feof expressions, so when you check $feof(STDIN), it sees that STDIN is a constant localparam and assumes that the expression must be as well.
When we do the constant propagation pass, we use this check to determine whether we can replace an expression by a constant. If you’ve got a check against $feof(STDIN), we assume it’s a constant and then blow away the else condition of the check and make sure that the if branch is always taken.
By creating a variable and assigning it to STDIN, you can get around this, because the expression technically isn’t a constant. Technically. If you declare a register and never assign a value to it, we really should be calling it a constant, but that’s beside the point.
Deliverables