vmware-archive / cascade

A Just-In-Time Compiler for Verilog from VMware Research
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A running list of bugs encountered on the way to pldi #195

Closed eschkufz closed 4 years ago

eschkufz commented 4 years ago

Overview

  1. ~Hierarchical references in named connection bindings cause an error:~
    Foo f(.clk(clock.val));
  2. ~For loops with identical iterator variables cause crashes:~
    integer i;
    for (i = 0; i < 2; i=i+1) ...
    for (i = 0; i < 2; i=i+1) ...
  3. ~namespace nesting for targets has bitrotted~
  4. ~16x16 nw benchmark uses 8x8 dataset~
  5. ~Many instances of 32 bit assumption still hard-coded in avmm backend~
  6. ~Building cascade as a library requires linking against libcascade and libverilog.~
  7. ~Many instances of path resolution are not correctly using the -I flag.~
  8. ~Errors in state machine transformation for programs with complex nestings of if/thens and case statements.~
  9. ~Errors in state machine generation for mix of always @() blocks (posedge clock vs posedge clock or posedge reset)~

Deliverables

eschkufz commented 4 years ago

For no particularly good reason, these bugs were all fixed in issue-190. We'll merge those changes shortly.