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A Just-In-Time Compiler for Verilog from VMware Research
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Incorrect assignment to uppercase hex literals #238

Open ynaffitgnay opened 4 years ago

ynaffitgnay commented 4 years ago

Overview

A variable is assigned the incorrect value when there are uppercase letters in the literal. An example to reproduce the problem can be found at https://github.com/ynaffitgnay/CascadeBenches/blob/master/bugreports/uppercase_hex_assignment.v

The current output is:

>>> ffffffffffffffed
>>> deaddeaddeaddead

It should be:

>>> deaddeaddeaddead
>>> deaddeaddeaddead