RX FIFO/s full during sequence

[zkjiang]

When I use the latest marcos_extras such as branch vn/mimo or a self compiled FPGA bit file, vn/clock_forward

the client's read function rxd, msgs = exp.run() plt.plot(np.abs(rxd["rx0"])) plt.plot(np.abs(rxd["rx1"]))

keeps popping up an error 'SERVER ERROR: RX FIFO/s full duration sequence around byte address 0x50c'

if I use the old marcos_extras - master it turns to normal and no error

when i Sample 2000 points in channel 1， Sample 3000 points in channel 2

[vnegnev]

Could you please post your experiment script, your marcos_client local_config file, and the exact marcos_client commit hash you're using? I'll see if I can reproduce this and investigate - I haven't seen any problems like this before.

[vnegnev]

Regarding your other question on marcos_fpga, there's a branch using @catkira's open-source cores ( https://github.com/vnegnev/marcos_fpga/tree/master ), and one using the Xilinx closed-source cores ( https://github.com/vnegnev/marcos_fpga/tree/rename-marga ). I plan to switch to using only the open-source cores, but want to make some HDL changes to the project structure beforehand so this may take a while longer. You need to make sure marcos_client is suitably configured for the bitstream version you are running, because the open-source cores need some additional configuration.

[zkjiang]

Thank you for such a timely response. In order to explian it clearly and to get help and collaboration, Please allow me to introduce our background. I am an assistant professor in China. I have read the code about marcos_client, marcos_server, marcos_fpga, copy_bitstream.sh, MaRGE and etc. In addition, we have prepared the hardware as shown in the figure below and successfully implemented the experiment. First Experiment: git clone from main branch of marcos_server, marcos_client, marcos_extras, MaRGE, and installed in my wsl2 of ubuntu20.04, it works Okay and Good. I think the pl example in fpga is marcos_fpga_rp-122.bit in marcos_extras git. Second Experiment: I want to change the fpga code. So it git clone the three branches of the marcos_fpga git, such as [master], [rename-marga] , [[vn/clock_forward]. The first can not built Okay , The second and the third can built Okay in vivado 2020.2 such as belows:

I tried 3 times by using three different bit to overcome old marcos_fpga_rp-122.bit in marcos_extras git 1) marcos_fpga.bit by make command 2) system_wrapper.bit by vivado three steps 3) marcos_fpga_rp-122.bit in vn/clock_forward branch in marcos_extras branch I want to konw the difference of these 3 bits? And I also want to try in another copy mode by coping marcos_fpga_rp-122.dtbo, marcos_fpga_rp-122.bit.bin, what is the difference?

when I use MaRGE and marcos_client it doesnot work okay when I tried in three conditions, I want to know which marcos_client and marcos_server can match. the marcos_experiment code is as belows to generate 2 signal form DA and receive 2 signal from AD selfsend and selfreceive. The result is as I showed the day before yesterday.

I want to find the reason of error, it turns to this code?

[vnegnev]

Hi, thanks for the extra details!

The code in event_dict looks okay - however you are acquiring data for 4ms on each channel, and the RX FIFOs in MaRCoS can only handle ~30,000 samples. What RX rate do you intend to acquire at? (Usually people use a maximum of a few hundred kHz.) In the first screenshot, the x axis shows 4000 samples, i.e. an acquisition rate of 1 MHz for a 4ms window. The second screenshot shows 12000 samples, which is 3 MHz - this is difficult for MaRCoS, and the system may struggle to keep up.

To isolate the problem I'd need to see your full marcos_experiment code as well as the local_config.py file in marcos_client. This would show me how the system is being configured (e.g. it might be due to the sampling rate you are using, or the configuration of the CIC decimators - if you are running at a high sampling rate, you will indeed fill up the RX FIFOs).

Regarding the FPGA bitstreams, rename-marga is the latest 'mainstream' code ( vn/clock_forward is a development branch which I don't support yet, and master uses the open-source cores which work well but need additional configuration). If you can successfully run the Makefile you will get .bit.bin and .dtbo files, which you can flash to the FPGA either manually or by having a look at the commands used in copy_bitstream.sh .

I tried 3 times by using three different bit to overcome old marcos_fpga_rp-122.bit in marcos_extras git

marcos_fpga.bit by make command
system_wrapper.bit by vivado three steps
marcos_fpga_rp-122.bit in vn/clock_forward branch in marcos_extras branch
I want to konw the difference of these 3 bits? And I also want to try in another copy mode by coping marcos_fpga_rp-122.dtbo, marcos_fpga_rp-122.bit.bin, what is the difference?

The only procedure I support is using the Makefile, which should run all the commands you need automatically and produce the .bit, the .bit.bin and the .dtbo files. If you use the original Red Pitaya SD card image with the SDRLab, you can flash the FPGA using the .bit file directly. If you use the customised SD card image from my Google Drive, you need to use the .bit.bin and .dtbo files. The SD card image may change soon, because I want to start programming the FPGA upon startup, rather than leaving it to the user.

There's also a Discord channel now for informal discussion of the system - let me know if you'd like an invite link.

[zkjiang]

env1.rar.zip env2.rar.zip env3.rar.zip env4.rar.zip @vnegnev

Thank you for inviting me . I am very gald to join this programe. I have tried many tests to rund fpga code , but unfortunately, they all failed，I have upload 4 tar file to include 4 envs to test. The stesp are all the same ./marcos_setup.sh 192.168.1.101 rp-122 ssh root@192.168.1.101 "~/marcos_server" run python first.py in the marcos_experiments folder

the difference of 4 envs are the marcos_fpga_rp-122.bit . In env1 it is in the https://github.com/vnegnev/marcos_extras In env2 it is in the -b vn/mimo In env3 it is got from https://github.com/vnegnev/marcos_fpga by makfile In env4 it is got from https://github.com/vnegnev/marcos_fpga by three steps synthesis implementation generator in vivado

The first is okay the othters are all fail

[vnegnev]

Sorry for the long delay! I should have time to investigate this after this week.