Fix PowerPC CPU detection and codegen to work with more processors.

[jhamby]

This patch defines the correct optional Power ISA features that the PPC code generator needs in order to run without crashing on v2.01 and older CPUs such as PPC 970 (G5) or NXP e6500, and to run more efficiently on CPUs with features that weren't being used before.

PowerPC ISA v2.01 and older CPUs don't have FP round to int instructions, and PowerPC ISA v2.06 and older are missing support for unsigned 64-bit to/from double, as well as integer to/from single-precision float.

Add a new FP_ROUND_TO_INT CPU feature to determine whether to generate FP round to int, and add a new PPC_7_PLUS feature to determine whether to use the v2.06 FPR conversion instructions or generate an alternate sequence to handle large 64-bit unsigned ints, and single-precision using the v2.01 instructions with handling for large uint64_t values as well as rounding results from double to single-precision.

Also add a new POP_COUNT feature for the popcnt opcodes added in v2.06, which are also present in the NXP e5500 and e6500 cores, which are otherwise missing many of the features added since v2.01.

By defining an ICACHE_SNOOP feature bit to replace the poorly-named "LWSYNC", the meaning of the instruction cache flushing fast path, and the CPUs that can use it, are more clearly defined. In addition, for the other PowerPC chips, the loop to flush the data and instruction cache blocks has been split into two loops, with a single "sync" and "isync" after each loop, which should be more efficient, and also handles the few CPUs with differing data and instruction cache line sizes.

In the macro assembler methods, in addition to providing an alternate path for FP conversion opcodes added in POWER7 (ISA v2.06), unnecessary instructions to move sp down and then immediately back up were replaced with negative offsets from the current sp. This should be faster, and also sp is supposed to point to a back chain at all times (V8 may not do this).

This patch also fixes ppc64 big-endian ELFv1 builds (not needed for Void).

Testing the changes

• I tested the changes in this PR: YES

Local build testing

• I built this PR locally for my native architecture, (ppc64-glibc)

[q66]

please fix commit messages to follow guidelines, probably squash the commits too

[q66]

also https://github.com/void-linux/void-packages/commit/0d70f0d2e2bf6004983c5efe6fb29ff7928bde52