Open yliu921 opened 4 months ago
Could you find anything on this?
In synthesis, 300MHz frequency is produced for ap_clk signal of VX_afu_wrap(). Even when I change configuration (#warps and #threads) before generating FPGA bitstream file, the clock frequency value remains the same (300MHz).
Hi, guys, I'm trying to change the frequency of the Vortex core in Alveo U50. However, I could not find the clock configuration in the Makefile. Does anyone know where I may overlook? Any idea will be appreciated:)