I used the automated make script to generate a Vivado project for FPGA implementation of Vortex. It creates the project however gives error during synthesis:
[Synth 8-2671] single value range is not allowed in this mode of verilog ["/vortex/build/hw/syn/xilinx/test/project_1/src/Vortex_top.v":51]
When I reconfig the file type as SystemVerilog, then behavioral simulation gives this error during elaboration phase:
[VRFC 10-2063] Module not found while processing module instance ["/vortex/build/hw/syn/xilinx/test/project_1/project_1.ip_user_files/bd/design_1/sim/design_1.v":131]
I used the automated make script to generate a Vivado project for FPGA implementation of Vortex. It creates the project however gives error during synthesis:
When I reconfig the file type as SystemVerilog, then behavioral simulation gives this error during elaboration phase: